Intel Xeon X3460 BX80605X3460 User Manual

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

109

31:14

RV

0

13

RW

0

CPUCSR_IB_Abort
This bit controls if inbound access to CPUCSR range is enabled.
0 = IB access to CPUCSR range is disabled, that is, allowed.

1 = IB access to CPUCSR range is enabled, that is, disallowed.

12

RW

0

Lock Thawing Mode
Mode controls how inbound queues in the south agents (PCIe, DMI) thaw 

when they are target of a locked read. 
0 = Thaw only posted requests

1 = Thaw posted and non-posted requests.

11:10

RW

00

SUBDECEN
Indicates the port that provides the subtractive decode path for inbound and 

outbound decode. 
00 = DMI
01 = Reserved
10 = Reserved
11 = Intel

 

QuickPath Interconnect

When this points to DMI, all address ranges in the PCI-to-PCI configuration 

space of the port are ignored for address decode purposes.

9

RV

0

8

RW

0

TOCMVALID 
This bit is set by software after it has initialized the TOCM register with the 

right value. IIO decoder uses this bit to determine if bits from 32 to TOCM are 

to be decoded towards privileged CSR space.

7:3

RO

00100

TOCM
Indicates the top of Intel

 

QuickPath Interconnect physical addressability limit.

00100 = 2^36 (default)
IIO uses this to abort all inbound transactions that cross this limit.

2

RW

0

EN1K
This bit when set, enables 1-K granularity for I/O space decode in each of the 

virtual PCI-to-PCI bridges corresponding to root ports and DMI ports.

1:0

RV

0