Intel Xeon X3460 BX80605X3460 User Manual

Product codes
BX80605X3460
Page of 296
Processor Integrated I/O (IIO) Configuration Registers
108
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.4.3.6
DEVSTS—PCI Express Device Status Register
The PCI Express Device Status register provides information about PCI Express device 
specific parameters associated with the device.
Device:
8
Function: 0, 1, 2
Offset:
4Ah
Bit
Attr
Default
Description
15:6
RO
000h
Reserved
5
RO
0h
Transactions Pending
0 = This bit cleared only when all Completions for any outstanding Non-
Posted Requests it owns have been received.
1 = Indicates that the DMA device has outstanding Non-Posted Request 
which it has issued either towards main memory or a peer PCI Express 
port, which have not been completed.
4
RO
0
Reserved
3
RO
0
Unsupported Request Detected
This bit applies only to the root/DMI ports.This bit indicates that the root 
port detected an Unsupported Request. Errors are logged in this register 
regardless of whether error reporting is enabled or not in the Device Control 
Register. 
0 = No unsupported request detected by the root port.
1 = Unsupported Request detected at the device/port. These unsupported 
requests are NP requests inbound that the root port received and it 
detected them as unsupported requests (for example, address decoding 
failures that the root port detected on a packet, receiving inbound lock 
reads, BME bit is clear and so forth). Note that this bit is not set on 
peer-to-peer completions with UR status that are forwarded by the root 
port to the PCI Express link.
2
RO
0
Fatal Error Detected
This bit applies only to the root/DMI ports. This bit indicates that a fatal 
(uncorrectable) error is detected by the device. Errors are logged in this 
register regardless of whether error reporting is enabled or not in the Device 
Control register. 
0 = No Fatal errors detected
1 = Fatal errors detected
1
RO 
0
Non Fatal Error Detected
This bit applies only to the root/DMI ports. This bit gets set if a non-fatal 
uncorrectable error is detected by the device. Errors are logged in this 
register regardless of whether error reporting is enabled or not in the Device 
Control register. 
0 = No non-Fatal Errors detected
1 = Non Fatal errors detected
0
RO
0
Correctable Error Detected
This bit applies only to the root/DMI ports. This bit gets set if a correctable 
error is detected by the device. Errors are logged in this register regardless 
of whether error reporting is enabled or not in the PCI Express Device 
Control register.
0 = No correctable errors detected
1 = Correctable errors detected