Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Processor Uncore Configuration Registers
198
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.4.3
RID—Revision Identification Register
This register contains the revision number of the processor. The Revision ID (RID) is a
traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI
header of every PCI/PCI Express compatible device and function.
traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI
header of every PCI/PCI Express compatible device and function.
Previously, a new value for RID was assigned for Intel chipsets for every stepping.
There is a a need to provide an alternative value for software compatibility when a
particular driver or patch unique to that stepping or an earlier stepping is required, for
instance, to prevent Windows software from flagging differences in RID during device
enumeration. The solution is to implement a mechanism to read one of two possible
values from the RID register:
There is a a need to provide an alternative value for software compatibility when a
particular driver or patch unique to that stepping or an earlier stepping is required, for
instance, to prevent Windows software from flagging differences in RID during device
enumeration. The solution is to implement a mechanism to read one of two possible
values from the RID register:
1. Stepping Revision ID (SRID): This is the default power on value for mask/metal
steppings
2. Compatible Revision ID (CRID): The CRID functionality gives BIOS the flexibility
to load OS drivers optimized for a previous revision of the silicon instead of the
current revision of the silicon in order to reduce drivers updates and minimize
changes to the OS image for minor optimizations to the silicon for yield
improvement, or feature enhancement reasons that do not negatively impact the
OS driver functionality.
current revision of the silicon in order to reduce drivers updates and minimize
changes to the OS image for minor optimizations to the silicon for yield
improvement, or feature enhancement reasons that do not negatively impact the
OS driver functionality.
Reading the RID in the processor returns either the SRID or CRID depending on the
state of a register select flip-flop. Following reset, the register select flip flop is reset
and the SRID is returned when the RID is read at offset 08h. The SRID value reflects
the actual product stepping. To select the CRID value, BIOS/configuration software
writes a key value of 69h to Bus 0, Device 0, Function 0 (DMI device) of the processor’s
RID register at offset 08h. This sets the SRID/CRID register select flip-flop and causes
the CRID to be returned when the RID is read at offset 08h.
state of a register select flip-flop. Following reset, the register select flip flop is reset
and the SRID is returned when the RID is read at offset 08h. The SRID value reflects
the actual product stepping. To select the CRID value, BIOS/configuration software
writes a key value of 69h to Bus 0, Device 0, Function 0 (DMI device) of the processor’s
RID register at offset 08h. This sets the SRID/CRID register select flip-flop and causes
the CRID to be returned when the RID is read at offset 08h.
The RID register in the DMI device (Bus 0 device 0 Function 0) is a “write-once” sticky
register and gets locked after the first write. This causes the CRID to be returned on all
subsequent RID register reads. Software should read and save all device SRID values
by reading processor device RID registers before setting the SRID/CRID register select
flip flop. The RID values for all devices and functions in the processor are controlled by
the SRID/CRID register select flip flop, thus writing the key value (69h) to the RID
register in Bus 0, Device 0, Function 0 sets all processor device RID registers to return
the CRID. Writing to the RID register of other devices has no effect on the SRID/CRID
register select flip-flop. Only a power good reset can change the RID selection back to
SRID.
register and gets locked after the first write. This causes the CRID to be returned on all
subsequent RID register reads. Software should read and save all device SRID values
by reading processor device RID registers before setting the SRID/CRID register select
flip flop. The RID values for all devices and functions in the processor are controlled by
the SRID/CRID register select flip flop, thus writing the key value (69h) to the RID
register in Bus 0, Device 0, Function 0 sets all processor device RID registers to return
the CRID. Writing to the RID register of other devices has no effect on the SRID/CRID
register select flip-flop. Only a power good reset can change the RID selection back to
SRID.