Intel Xeon X3460 BX80605X3460 User Manual

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Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

SMI DIMM error threshold overflow status register. This bit is set when the per-DIMM 
error counter exceeds the specified threshold. The bit is reset by BIOS.

System Management Interrupt control register.

31:14

RO

0

13:12

RW0C

0

REDUNDANCY_LOSS_FAILING_DIMM. The ID for the failing DIMM when 

redundancy is lost.

11:8

Reserved

7:0

RW0C

0

DIMM_ERROR_OVERFLOW_STATUS. This 8-bit field is the per DIMM error 

overflow status bits. The organization is as follows:
If there are three or more DIMMS on the channel:
Bit 0 = DIMM 0 Channel 0 
Bit 1 = DIMM 1 Channel 0 
Bit 2 = DIMM 2 Channel 0 
Bit 3 = DIMM 3 Channel 0 
Bit 4 = DIMM 0 Channel 1 
Bit 5 = DIMM 1 Channel 1 
Bit 6 = DIMM 2 Channel 1 
Bit 7 = DIMM 3 Channel 1 

If there are one or two DIMMS on the channel: 
Bit 0 = DIMM 0, Ranks 0 and 1, Channel 0 
Bit 1 = DIMM 0, Ranks 2 and 3, Channel 0 
Bit 2 = DIMM 1, Ranks 0 and 1, Channel 0 
Bit 3 = DIMM 1, Ranks 2 and 3, Channel 0 
Bit 4 = DIMM 0, Ranks 0 and 1, Channel 1 
Bit 5 = DIMM 0, Ranks 2 and 3, Channel 1 
Bit 6 = DIMM 1, Ranks 0 and 1, Channel 1 
Bit 7 = DIMM 1, Ranks 2 and 3, Channel 1 

31:17

RO

0

16

RW

0

INTERRUPT_SELECT_NMI 
NMI enable. Set to enable NMI signaling. Clear to disable NMI signaling. If both 

NMI and SMI enable bits are set, then only SMI is sent.

15

RW

0

INTERRUPT_SELECT_SMI 
SMI enable. Set to enable SMI signaling. Clear to disable SMI signaling. If both 

NMI and SMI enable bits are set, then only SMI is sent. 

14:0

RW

0

SMI_ERROR_THRESHOLD 
Defines the error threshold to compare against the per-DIMM error counters 

MC_COR_ECC_CNT_X, which are also 15 bits.