Intel Xeon X3460 BX80605X3460 User Manual

Product codes
BX80605X3460
Page of 296
Processor Uncore Configuration Registers
218
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.7.6
MC_CHANNEL_MAPPER
Channel mapping register. The sequence of operations to update this register is:
Read MC_Channel_Mapper register
Compare data read to data to be written. If different then write.
Poll MC_Channel_Mapper register until the data read matches data written.
 
4.7.7
MC_MAX_DOD
This register defines the MAX number of DIMMS, RANKS, BANKS, ROWS, COLS among 
all DIMMS populating the two channels. The Memory Init logic uses this register to 
cycle through all the memory addresses writing all 0s to initialize all locations.
Device:
3
Function: 0
Offset:
60h
Access as a DWord
Bit
Attr
Default
Description
31:12
RO
0
Reserved
11:9
RW
0
RDLCH1
Mapping of Logical channel 1 to physical channel for Reads.
8:6
RW
0
WRLCH1
Mapping of Logical channel 1 to physical channel for Writes.
5:3
RW
0
RDLCH0
Mapping of Logical channel 0 to physical channel for Read.
2:0
RW
0
WRLCH0
Mapping of Logical channel 0 to physical channel for Writes.
Device:
3
Function: 0
Offset:
64h
Access as a DWord
Bit
Attr
Default
Description
31:11
RO
0
Reserved
10:9
RW
0
MAXNUMCOL
Maximum Number of Columns.
00 = 2^10 columns
01 = 2^11 columns
10 = 2^12 columns
11 = Reserved
8:6
RW
0
MAXNUMROW
Maximum Number of Rows.
000 = 2^12 Rows
001 = 2^13 Rows
010 = 2^14 Rows
011 = 2^15 Rows
100 = 2^16 Rows
Others = Reserved.