Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Configuration Process and Registers
22
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
the base address for the block of addresses below 4 GB for the configuration space
associated with busses, devices and functions that are potentially a part of the PCI
Express root complex hierarchy. In the SAD_PCIEXBAR register there exists controls to
limit the size of this reserved memory mapped space. 256 MB is the amount of address
space required to reserve space for every bus, device, and function that could possibly
exist. Options for 128 MB and 64 MB exist in order to free up those addresses for other
uses. In these cases the number of busses and all of their associated devices and
functions are limited to 128 or 64 busses, respectively.
associated with busses, devices and functions that are potentially a part of the PCI
Express root complex hierarchy. In the SAD_PCIEXBAR register there exists controls to
limit the size of this reserved memory mapped space. 256 MB is the amount of address
space required to reserve space for every bus, device, and function that could possibly
exist. Options for 128 MB and 64 MB exist in order to free up those addresses for other
uses. In these cases the number of busses and all of their associated devices and
functions are limited to 128 or 64 busses, respectively.
The PCI Express Configuration Transaction Header includes an additional four bits
(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all zeros.
(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all zeros.
As with PCI devices, each device is selected based on decoded address information that
is provided as a part of the address portion of Configuration Request packets. A PCI
Express device will decode all address information fields (bus, device, function and
extended address numbers) to provide access to the correct register.
is provided as a part of the address portion of Configuration Request packets. A PCI
Express device will decode all address information fields (bus, device, function and
extended address numbers) to provide access to the correct register.
To access this space (step 1 is done only once by BIOS),
1. Write to CSR address 01050h to enable the PCI Express enhanced configuration
mechanism by writing 1 to Bit 0 of the SAD_PCIEXBAR register. Allocate either 256,
128, or 64 busses to PCI Express by writing “000”, “111”, or “110,” respectively, to
Bits 3:1. Pick a naturally aligned base address for mapping the configuration space
onto memory space using 1 MB per bus number and write that base address into
Bits 39:20.
2. Calculate the host address of the register you wish to set using (PCI Express base
+ (bus number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) +
(1 B * offset within the function) = host address).
(1 B * offset within the function) = host address).
3. Use a memory write or memory read cycle to the calculated host address to write
or read that register.
Figure 2-1. Memory Map to PCI Express* Device Configuration Space
Bus 0
Bus 1
Bus 255
Device 0
Device 1
0
0xFFFFF
0x1FFFFF
0xFFFFFFF
0x7FFF
0xFFFF
0xFFFFF
Located by
PCI Express* Base Address
Device 31
Function 0
Function 1
0xFFF
0x1FFF
0x7FFF
Function 7
PCI Compatible
Configuration
Space Header
0x3F
0xFFF
PCI Express
Extended
Configuration
Space
PCI Compatible
Configuration
Space
0xFF