Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Configuration Process and Registers
24
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
2.3.1
Internal Device Configuration Accesses
The processor decodes the Bus Number (Bits 23:16) and the Device Number fields of
the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a PCI Bus 0 device.
the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a PCI Bus 0 device.
If the targeted PCI Bus 0 device exists in the processor and is not disabled, the
configuration cycle is claimed by the appropriate device.
configuration cycle is claimed by the appropriate device.
2.3.2
Bridge-Related Configuration Accesses
Configuration accesses on PCI Express or DMI are PCI Express Configuration
Transaction Layer Packets (TLPs).
Transaction Layer Packets (TLPs).
• Bus Number [7:0] is Header Byte 8 [7:0]
• Device Number [4:0] is Header Byte 9 [7:3]
• Function Number [2:0] is Header Byte 9 [2:0]
• Device Number [4:0] is Header Byte 9 [7:3]
• Function Number [2:0] is Header Byte 9 [2:0]
And special fields for this type of TLP:
• Extended Register Number [3:0] is Header Byte 10 [3:0]
• Register Number [5:0] is Header Byte 11 [7:2]
• Register Number [5:0] is Header Byte 11 [7:2]
See the PCI Express Specification for more information on both the PCI 2.3 compatible
and PCI Express Enhanced Configuration Mechanism and transaction rules.
and PCI Express Enhanced Configuration Mechanism and transaction rules.
2.3.2.1
PCI Express* Configuration Accesses
When the Bus Number of a Type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access matches the Device 1 Secondary Bus Number a PCI
Express Type 0 Configuration TLP is generated on the PCI Express link targeting the
device directly on the opposite side of the link. This should be Device 0 on the bus
number assigned to the PCI Express link (likely Bus 1).
Enhanced Configuration access matches the Device 1 Secondary Bus Number a PCI
Express Type 0 Configuration TLP is generated on the PCI Express link targeting the
device directly on the opposite side of the link. This should be Device 0 on the bus
number assigned to the PCI Express link (likely Bus 1).
The device on other side of link must be Device 0. The processor will Master Abort any
Type 0 Configuration access to a non-zero Device number. If there is to be more than
one device on that side of the link there must be a bridge implemented in the
downstream device.
Type 0 Configuration access to a non-zero Device number. If there is to be more than
one device on that side of the link there must be a bridge implemented in the
downstream device.
When the Bus Number of a Type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access is within the claimed range (between the upper bound
of the bridge device’s Subordinate Bus Number register and the lower bound of the
bridge device’s Secondary Bus Number register) but doesn't match the Device 1
Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the
secondary side of the PCI Express link.
Enhanced Configuration access is within the claimed range (between the upper bound
of the bridge device’s Subordinate Bus Number register and the lower bound of the
bridge device’s Secondary Bus Number register) but doesn't match the Device 1
Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the
secondary side of the PCI Express link.
PCI Express Configuration Writes:
• The processor will translate writes to PCI Express extended configuration space to
configuration writes on the backbone internally.
• Posted writes to extended space are non-posted on the PCI Express or DMI (that is,
translated to configuration writes).