Intel S5000XAL BB5000XALR User Manual

a total read bandwidth of 21GB/s for four FB-DIMM channels. Thus, this provides 10.7 GB/s of write 
memory bandwidth for four FB-DIMM channels. The total bandwidth is based on read bandwidth thus the 
total bandwidth is 17 GB/s for 533 and 21.0 GB/s for 667. 

On the Intel® Server Board S5000PAL / S5000XAL, a pair of channels becomes a branch where Branch 
0 consists of channels A and B, and Branch 1 consists of channels C and D.  FBD memory channels are 
organized into two branches for support of RAID 1(mirroring). 

TP02299

DIMM D2

DIMM D1

DIMM C2

DIMM C1

DIMM B2

DIMM B1

DIMM A2

DIMM A1

Branch 0

MCH

Channel A

Channel B

Channel D

Channel C

Branch 1

 

 

To boot the system, the system BIOS on the server board uses a dedicated I

2

C bus to retrieve DIMM 

information needed to program the MCH memory registers. The following table provides the I

2

C 

addresses for each DIMM slot. 

DIMM A1

0xA0 

DIMM A2

0xA2 

DIMM B1

0xA0 

DIMM B2

0xA2 

DIMM C1

0xA0 

DIMM C2

0xA2 

DIMM D1

0xA0 

DIMM D2

0xA2 

The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and 
Manageability) features.  These features include the Intel

®

 x4 Single Device Data Correction (Intel

®

 x4 

SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors, 
Memory Built In Self Test, DIMM Sparing, and Memory Mirroring.  See the Intel

 for more information describing these features. 

The server board supports up to eight DDR2-533 or DDR2-667 Fully Buffered DIMMs (FBD memory).   
The following tables show the maximum memory configurations supported using the specified memory 
technology.