Intel W3530 AT80601000897AB User Manual
Product codes
AT80601000897AB
Thermal Specifications
88
Intel® Xeon® Processor 3500 Series Datasheet Volume 1
). THERMTRIP# activation is independent of processor activity. The
temperature at which THERMTRIP# asserts is not user configurable and is not software
visible.
visible.
6.3
Platform Environment Control Interface (PECI)
6.3.1
Introduction
The Platform Environment Control Interface (PECI) is a one-wire interface that provides
a communication channel between Intel processor and chipset components to external
monitoring devices. The processor implements a PECI interface to allow communication
of processor thermal and other information to other devices on the platform. The
processor provides a digital thermal sensor (DTS) for fan speed control. The DTS is
calibrated at the factory to provide a digital representation of relative processor
temperature. Instantaneous temperature readings from the DTS are available via the
IA32_THERM_STATUS MSR; averaged DTS values are read via the PECI interface.
a communication channel between Intel processor and chipset components to external
monitoring devices. The processor implements a PECI interface to allow communication
of processor thermal and other information to other devices on the platform. The
processor provides a digital thermal sensor (DTS) for fan speed control. The DTS is
calibrated at the factory to provide a digital representation of relative processor
temperature. Instantaneous temperature readings from the DTS are available via the
IA32_THERM_STATUS MSR; averaged DTS values are read via the PECI interface.
The PECI physical layer is a self-clocked one-wire bus that begins each bit with a
driven, rising edge from an idle level near zero volts. The duration of the signal driven
high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes
variable data transfer rate established with every message. The single wire interface
provides low board routing overhead for the multiple load connections in the congested
routing area near the processor and chipset components. Bus speed, error checking,
and low protocol overhead provides adequate link bandwidth and reliability to transfer
critical device operating conditions and configuration information.
driven, rising edge from an idle level near zero volts. The duration of the signal driven
high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes
variable data transfer rate established with every message. The single wire interface
provides low board routing overhead for the multiple load connections in the congested
routing area near the processor and chipset components. Bus speed, error checking,
and low protocol overhead provides adequate link bandwidth and reliability to transfer
critical device operating conditions and configuration information.
6.3.1.1
Fan Speed Control with Digital Thermal Sensor
Fan speed control solutions use a value stored in the static variable, T
CONTROL
. The DTS
temperature data which is delivered over PECI (in response to a GetTemp0()
command) is compared to this T
command) is compared to this T
CONTROL
reference. The DTS temperature is reported as
a relative value versus an absolute value. The temperature reported over PECI is
always a negative value and represents a delta below the onset of thermal control
circuit (TCC) activation, as indicated by PROCHOT#. Therefore, as the temperature
approaches TCC activation, the value approaches zero degrees.
always a negative value and represents a delta below the onset of thermal control
circuit (TCC) activation, as indicated by PROCHOT#. Therefore, as the temperature
approaches TCC activation, the value approaches zero degrees.
6.3.1.2
Processor Thermal Data Sample Rate and Filtering
The processor digital thermal sensor (DTS) provides an improved capability to monitor
device hot spots, which inherently leads to more varying temperature readings over
short time intervals. To reduce the sample rate requirements on PECI and improve
thermal data stability vs. time the processor DTS implements an averaging algorithm
that filters the incoming data. This filter is expressed mathematically as:
device hot spots, which inherently leads to more varying temperature readings over
short time intervals. To reduce the sample rate requirements on PECI and improve
thermal data stability vs. time the processor DTS implements an averaging algorithm
that filters the incoming data. This filter is expressed mathematically as:
PECI(t) = PECI(t–1)+1/(2^^X)*[Temp – PECI(t–1)]
Where: PECI(t) is the new averaged temperature, PECI(t-1) is the previous averaged
temperature Temp is the raw temperature data from the DTS, X is the Thermal
Averaging Constant (TAC)
temperature Temp is the raw temperature data from the DTS, X is the Thermal
Averaging Constant (TAC)
Note:
Only values read via the PECI interface are averaged. Temperature values read via the
IA32_THERM_STATUS MSR are not averaged.
The Thermal Averaging Constant is a BIOS configurable value that determines the time
in milliseconds over which the DTS temperature values are averaged. Short averaging
times will make the averaged temperature values respond more quickly to DTS
in milliseconds over which the DTS temperature values are averaged. Short averaging
times will make the averaged temperature values respond more quickly to DTS