Intel W3530 AT80601000897AB User Manual
Product codes
AT80601000897AB
Intel® Xeon® Processor 3500 Series Datasheet Volume 1
89
Thermal Specifications
changes. Long averaging times will result in better overall thermal smoothing but also
incur a larger time lag between fast DST temperature changes and the value read via
PECI. Refer to the appropriate processor Thermal and Mechanical Design Guidelines
(see
incur a larger time lag between fast DST temperature changes and the value read via
PECI. Refer to the appropriate processor Thermal and Mechanical Design Guidelines
(see
) for further details on the Data Filter and the Thermal Averaging
Constant.
Within the processor, the DTS converts an analog signal into a digital value
representing the temperature relative to TCC activation. The conversions are in
integers with each single number change corresponding to approximately 1 °C. DTS
values reported via the internal processor MSR will be in whole integers.
representing the temperature relative to TCC activation. The conversions are in
integers with each single number change corresponding to approximately 1 °C. DTS
values reported via the internal processor MSR will be in whole integers.
As a result of the averaging function described above, DTS values reported over PECI
will include a 6 bit fractional value. Under typical operating conditions, where the
temperature is close to Tcontrol, the fractional values may not be of interest. But when
the temperature approaches zero, the fractional values can be used to detect the
activation of the TCC. An averaged temperature value between 0 and 1 can only occur
if the TCC has been activated during the averaging window. As TCC activation time
increases, the fractional value will approach zero. Fan control circuits can detect this
situation and take appropriate action as determined by the system designers. Of
course, fan control chips can also monitor the Prochot pin to detect TCC activation via a
dedicated input pin on the package. Further details on how the Thermal Averaging
Constant influences the fractional temperature values are available in the Thermal
Design Guide.
will include a 6 bit fractional value. Under typical operating conditions, where the
temperature is close to Tcontrol, the fractional values may not be of interest. But when
the temperature approaches zero, the fractional values can be used to detect the
activation of the TCC. An averaged temperature value between 0 and 1 can only occur
if the TCC has been activated during the averaging window. As TCC activation time
increases, the fractional value will approach zero. Fan control circuits can detect this
situation and take appropriate action as determined by the system designers. Of
course, fan control chips can also monitor the Prochot pin to detect TCC activation via a
dedicated input pin on the package. Further details on how the Thermal Averaging
Constant influences the fractional temperature values are available in the Thermal
Design Guide.
6.3.2
PECI Specifications
6.3.2.1
PECI Device Address
The PECI register resides at address 30h.
6.3.2.2
PECI Command Support
The processor supports the PECI commands listed in
6.3.2.3
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive. Prior to a power
on RESET# and during RESET# assertion, PECI is not ensured to provide reliable
thermal data. System designs should implement a default power-on condition that
ensures proper processor operation during the time frame when reliable data is not
available via PECI.
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive. Prior to a power
on RESET# and during RESET# assertion, PECI is not ensured to provide reliable
thermal data. System designs should implement a default power-on condition that
ensures proper processor operation during the time frame when reliable data is not
available via PECI.
Table 6-4.
Supported PECI Command Functions and Codes
Command
Function
Code
Comments
Ping()
n/a
This command targets a valid PECI device address followed by zero
Write Length and zero Read Length.
Write Length and zero Read Length.
GetTemp0()
01h
Write Length: 1
Read Length: 2
Returns the temperature of the processor in Domain 0
Read Length: 2
Returns the temperature of the processor in Domain 0