Intel AT80604004872AA User Manual
Electrical Specifications
48
Intel® Xeon® Processor 7500 Datasheet, Volume 1
Notes:
1.
See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design
Guidelines for addition information.
2.
Platform support for VID transitions is required for the processor to operate within specifications.
3.
Inspection range is VIL Max to VIH Min. When a signal ledge presents between VIL and VIH region, measure the first edge
rate from VIL (or VIH) to the first inflection point, then measure the second edge rate from the second inflection point to VIH
(or VIL) and divide the two edge rates by two, to generate the final edge rate number.
4.
Error[0]_N edge min edge rate may be as low as 0.05 V/ns if the edge is monotonic.
5.
For production platforms, reset determinism is not required.
Table 2-28. VID Signal Group AC Specifications
T # Parameter
Min
Max
Unit
Figure
Notes
1, 2
VID Step Time
-
-
µs
VID Down Transition to Valid V
CCP
(min)
-
-
µs
VID Up Transition to Valid V
CCP
(min)
-
-
µs
VID Down Transition to Valid V
CCP
(max)
-
-
µs
VID Up Transition to Valid V
CCP
(max)
-
-
µs
Figure 2-11. RESET_N SEtup/Hold Time for Deterministic RESET_N Deassertion
Thold
Tsetup
RESET_N
SYSCLK_N
SYSCLK
V
IL
V
IH
Note: Deterministic RESET_N is defined for RESET_N deassertion only (coming out of RESET_N)
Figure 2-12. THERMTRIP_N Power Down Sequence
T
A
= THERMTRIP_N assertion until V
CC
and V
CACHE
removal
THERMTRIP_N
V
CC,
V
CACHE
T
A