Intel AT80604004872AA User Manual
Intel® Xeon® Processor 7500 Datasheet, Volume 1
49
Electrical Specifications
Figure 2-13. VID Step Times
Table 2-29. SMBus and SPDBus Signal Group AC Timing Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes
1,2
Notes:
1. These parameters are based on design characterization and are not tested.
2.
All AC timings for the SMBus signals are referenced at V
IL_MAX
or V
IL_MIN
and measured at the
processor pins. Refer to
.
Transmitter and Receiver Timings
F
SMB
SMBCLK Frequency
10
100
kHz
TCK
SMBCLK Period
10
100
µs
t
LOW
SMBCLK High Time
4
µs
t
HIGH
SMBCLK Low Time
4.7
µs
t
R
SMBus Rise Time
1
µs
3
3. Rise time is measured from (V
IL_MAX
- 0.15V) to (V
IH_MIN
+ 0.15V). Fall time is measured from
(0.9 * VCC33) to (V
IL_MAX
- 0.15V).
t
F
SMBus Fall Time
0.3
µs
T
AA
SMBus Output Valid Delay
0.1
4.5
µs
t
SU;DAT
SMBus Input Setup Time
250
ns
t
HD;DAT
SMBus Input Hold Time
0
ns
Vil, SMBus
SMBus Vil
-0.3
Vcc33 x 0.3
V
Vih, SMBus
SMBus Vih
Vcc33 x 0.7
Vcc33 + 0.5
V
Vol, SMBus
SMBus Vol Vcc >2.5
0.4
V
SMBus Vol Vcc <= 2.5
0.2
V
t
BUF
Bus Free Time between
Stop and Start Condition
4.7
µs
4,5
4. Minimum time allowed between request cycles.
5. Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next
transaction.
t
HD;STA
Hold Time after Repeated
Start Condition
4.0
µs
t
SU;STA
Repeated Start Condition
Setup Time
4.7
µs
t
SU;STD
Stop Condition Setup Time
4.0
µs
VID
n
n-1
m+1
m
...
Ta
Tb
Tc
Td
Ta = VID Down to Valid V
CC
(max)
Tb = VID Down to Valid V
CC
(min)
Tc = VID Up to Valid V
CC
(max)
Td = VID Up to Valid V
CC
(min)
V
CC
(max)
V
CC
(min)