Intel L5310 HH80563JH0258M Data Sheet

Product codes
HH80563JH0258M
Page of 124
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
99
Thermal Specifications
configurable and is not software visible. Bus traffic is snooped in the normal manner, 
and interrupt requests are latched (and serviced during the time that the clocks are on) 
while the TCC is active.
When the TM1 is enabled, and a high temperature situation exists (that is, TCC is 
active), the clocks will be modulated by alternately turning off and on at a duty cycle 
specific to the processor (typically 30 - 50%). Cycle times are processor speed 
dependent and will decrease as processor core frequencies increase. A small amount of 
hysteresis has been included to prevent rapid active/inactive transitions of the TCC 
when the processor temperature is near its maximum operating temperature. Once the 
temperature has dropped below the maximum operating temperature, and the 
hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
With thermal solutions designed to the Quad-Core Intel® Xeon® Processor E5300  
Thermal Profile, the Quad-Core Intel® Xeon® Processor L5300 Series Thermal Profile, 
Quad-Core Intel® Xeon® Processor X5365 Series Thermal Profile, or Quad-Core 
Intel® Xeon® Processor X5300 Series Thermal Profile A it is anticipated that the TCC 
would only be activated for very short periods of time when running the most power 
intensive applications. The processor performance impact due to these brief periods of 
TCC activation is expected to be so minor that it would be immeasurable. A thermal 
solution that is designed to Quad-Core Intel® Xeon® Processor X5300 Series Thermal 
Profile B may cause a noticeable performance loss due to increased TCC activation. 
Thermal Solutions that exceed Thermal Profile B will exceed the maximum temperature 
specification and affect the long-term reliability of the processor. In addition, a thermal 
solution that is significantly under designed may not be capable of cooling the 
processor even when the TCC is active continuously Refer to the Quad-Core Intel® 
Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines 
for information on 
designing a thermal solution.
The duty cycle for the TCC, when activated by the TM1, is factory configured and 
cannot be modified. The TM1 does not require any additional hardware, software 
drivers, or interrupt handling routines.
6.3.3
Thermal Monitor 2
The Quad-Core Intel® Xeon® Processor 5300 Series adds support for an Enhanced 
Thermal Monitor capability known as Thermal Monitor 2 (TM2). This mechanism 
provides an efficient means for limiting the processor temperature by reducing the 
power consumption within the processor. TM2 requires support for dynamic VID 
transitions in the platform.
When TM2 is enabled, and a high temperature situation is detected, the Thermal 
Control Circuit (TCC) will be activated for all processor cores. The TCC causes the 
processor to adjust its operating frequency (via the bus multiplier) and input voltage 
(via the VID signals). This combination of reduced frequency and VID results in a 
reduction to the processor power consumption.
A processor enabled for TM2 includes two operating points, each consisting of a specific 
operating frequency and voltage, which is identical for both processor dies. The first 
operating point represents the normal operating condition for the processor. Under this 
condition, the core-frequency-to-system-bus multiplier utilized by the processor is that 
contained in the CLOCK_FLEX_MAX MSR and the VID that is specified in 
The second operating point consists of both a lower operating frequency and voltage. 
The lowest operating frequency is determined by the lowest supported bus ratio (1/6 
for the Quad-Core Intel® Xeon® Processor 5300 Series). When the TCC is activated, 
the processor automatically transitions to the new frequency. This transition occurs