Intel Xeon 7130N LF80550KF0878M Data Sheet
Product codes
LF80550KF0878M
Electrical Specifications
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
31
NOTES:
1. All outputs are open drain.
2. The V
2. The V
TT
represented in these specifications refers to instantaneous V
TT
.
3. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
4. V
HYS
represents the amount of hysteresis, nominally centered about 0.5 * V
TT
for all PWRGOOD and TAP
inputs.
§
I
OL
Output Leakage Current
N/A
±200
µA
R
ON
Buffer On Resistance
4
8
Ω
Table 2-15. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
Table 2-16.
GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications
DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage
0.0
GTLREF – (0.10 * V
TT
)
V
2,
3
2. The V
TT
represented in these specifications refers to instantaneous V
TT
.
3. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
V
IH
Input High Voltage
GTLREF +(0.10 * V
TT
)
V
TT
V
4
4. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
V
OH
Output High Voltage
0.90 * V
TT
V
TT
V
I
OL
Output Low Current
N/A
50
mA
5
to determine which signals include additional on-die termination resistance (R
L
).
I
LI
Input Leakage Current
N/A
±200
µA
6,
7
6. Leakage to V
SS
with pin held at V
TT
.
7. Leakage to V
TT
with pin held at 300 mV.
I
LO
Output Leakage Current
N/A
±200
µA
R
on
Buffer On Resistance
4
8
Ω
Table 2-17. SMBus Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1, 2
NOTES:
1. These parameters are based on design characterization and are not tested.
2. All DC specifications for the SMBus signal group are measured at the processor pins.
1. These parameters are based on design characterization and are not tested.
2. All DC specifications for the SMBus signal group are measured at the processor pins.
V
IL
Input Low Voltage
-0.30
0.30 * SM_VCC
V
V
IH
Input High Voltage
0.70 * SM_VCC
3.465
V
V
OL
Output Low Voltage
0
0.400
V
I
OL
Output Low Current
N/A
3.0
mA
I
LI
Input Leakage Current
N/A
±
10
µA
I
LO
Output Leakage Current
N/A
±
10
µA
C
SMB
SMBus Pin Capacitance
15.0
pF
3
3. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
maximum rise and fall times for SMBus signals.