Intel Xeon 7130N LF80550KF0878M Data Sheet

74

HALT is a low power state entered when the processor executes the HALT instruction. The 
processor transitions to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] 
(NMI, INTR), or an interrupt delivered over the FSB. RESET# causes the processor to 
immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or 
the HALT Power Down state. See the IA-32 Intel

Volume III: System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When 
the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT state.

While in HALT Power Down state, the processor processes bus snoops and interrupts.

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks 
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. For the 
Dual-Core Intel Xeon processor 7000 series, both logical processors must be in the Stop-Grant 
state before the deassertion of STPCLK#.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven 
(allowing the level to return to V

TT

) for minimum power drawn by the termination resistors in this 

state. In addition, all other input pins on the FSB should be driven to the inactive state.

BCLK running
Snoops and interrupts allowed

Normal execution

BCLK running
Service snoops to caches

BCLK running
Snoops and interrupts allowed

Snoop

Event

Occurs

Snoop

Event

Serviced

INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts

STPCLK#
Asserted

STPCLK#
De-asserted

S

TP

C

LK

#

A

ss

er

te

d

S

TP

C

LK

#

D

e-

as

se

rte

d

Snoop Event Occurs

Snoop Event Serviced

HALT or MWAIT Instruction and
HALT Bus Cycle Generated

BCLK running
Service snoops to caches