Intel Xeon 7130N LF80550KF0878M Data Sheet

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BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched and can be 
serviced by software upon exit from the Stop-Grant state.

RESET# causes the processor to immediately initialize itself, but the processor will stay in 
Stop-Grant state. A transition back to the Normal state occurs with the deassertion of the 
STPCLK# signal.

A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the FSB 
(see 

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] are latched by the processor, 
and only serviced when the processor returns to the Normal state. Only one occurrence of each 
event is recognized upon return to the Normal state.

While in Stop-Grant state, the processor processes snoops on the FSB and latches interrupts 
delivered on the FSB.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is asserted if there 
is any pending interrupt latched within the processor. Pending interrupts that are blocked by the 
EFLAGS.IF bit being clear still cause assertion of PBE#. Assertion of PBE# indicates to system 
logic that it should return the processor to the Normal state.

The processor responds to snoop or interrupt transactions on the FSB while in Stop-Grant state or 
in HALT Power Down state. During a snoop or interrupt transaction, the processor enters the 
HALT/Grant Snoop state. The processor stays in this state until the snoop on the FSB has been 
serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. 
After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant 
state or HALT Power Down state, as appropriate.

Enhanced HALT state is a low power state entered when all logical processors have executed the 
HALT or MWAIT instruction and Enhanced HALT state has been enabled via the BIOS. When one 
of the logical processors executes the HALT instruction, that logical processor is halted; however, 
the other processor continues normal operation. The Enhanced HALT state is generally a lower 
power state than the Stop Grant state.

The processor will automatically transition to a lower core frequency and voltage operating point 
before entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; 
only the internal core frequency is changed. When entering the low power state, the processor will 
first switch to the lower bus ratio and then transition to the lower VID.

While in the Enhanced HALT state, the processor will process bus snoops.

The processor exits the Enhanced HALT state when a break event occurs. When the processor 
exists the Enhanced HALT state, it will first transition the VID to the original value and then 
change the bus ratio back to the original value.