Intel Xeon 7130N LF80550KF0878M Data Sheet

77

The processor SMBus implementation uses the clock and data signals of the System Management 
Bus (SMBus) Specification. It does not implement the SMBSUS# signal. Layout and routing 
guidelines are available in the appropriate platform design guide document.

For platforms which do not implement any of the SMBus features found on the processor, all of the 
SMBus connections, except SM_VCC, to the socket pins may be left unconnected (SM_ALERT#, 
SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP).

NOTE: Actual implementation may vary. This figure is provided to offer a general understanding of the 

architecture. All SMBus pull-up and pull-down resistors are 10 k

Ω and located on the processor.

The lower half (128 bytes) of the SMBus memory component is an electrically programmed 
read-only memory with information about the processor. This information is permanently 
write-protected. 

 shows the data fields and formats provided in the Processor Information 

ROM (PIROM). This is PIROM data format revision 2 (Offset 00). Fields which have changed 
for this revision are marked in italics in 

SM_EP_A1

Processor

Information

ROM

and

Scratch

EEPROM

(1 Kbit each)

Thermal

Sensor

A0

A1

A2

WP

A0

A1

SM_EP_A0

SM_EP_A2

SM_TS_A0

SM_TS_A1

SM_VCC

CLK

CLK

DATA

DATA

VCC

VCC

VSS

VSS

STDBY#

ALERT#

SM_CLK

SM_DAT

SM_ALERT#

SM_WP