Intel Xeon 7130N LF80550KF0878M Data Sheet

80

Also available in the memory component on the processor SMBus is an EEPROM which may be 
used for other data at the system or processor vendor’s discretion. The data in this EEPROM, once 
programmed, can be write-protected by asserting the active-high SM_WP signal. This signal has a 
weak pull-down (10 k

Ω) to allow the EEPROM to be programmed in systems with no 

implementation of this signal. The Scratch EEPROM resides in the upper half of the memory 
component (addresses 80 - FFh). The lower half comprises the Processor Information ROM 
(addresses 00 - 7Fh), which is permanently write-protected by Intel.

The Processor Information ROM (PIROM) responds to two SMBus packet types: Read Byte and 
Write Byte. However, since the PIROM is write-protected, it will acknowledge a Write Byte 
command but ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte 
commands. 

 diagrams the Read Byte command. 

 diagrams the Write Byte 

command. Following a write cycle to the scratch ROM, software must allow a minimum of 10 ms 
before accessing either ROM of the processor.

In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents a read bit, 
‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’ represents a negative 
acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or 
Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host controller. In 
the tables, the data addresses indicate 8 bits. The SMBus host controller should transmit 8 bits with 
the most significant bit indicating which section of the EEPROM is to be addressed: the Processor 
Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).

7Ah

8

[7] = Reserved
[6] = Reserved
[5] = Enhanced Halt State
[4] = Intel

7B-7Ch

16

[15:8] Measurement Correction Factor

[7:0] Temperature Target

7D- 7Eh

16

Reserved

Reserved

1

7-bits

1

1

8-bits

1

1

7-bits

1

1

8-bits

1

1