Intel Xeon 7130N LF80550KF0878M Data Sheet
Product codes
LF80550KF0878M
Features
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
81
7.4.4
SMBus Thermal Sensor
The processor’s SMBus thermal sensor provides a means of acquiring thermal data from the
processor. The thermal sensor is composed of control logic, SMBus interface logic, precision
analog-to-digital converters, and precision current sources. The sensor drives a small current
through the p-n junction of a thermal diode located on each processor core. The forward bias
voltage generated across the thermal diode is sensed and the precision A/D converter derives a
single byte of thermal reference data, or a “thermal byte reading.” The nominal precision of the
least significant bit of a thermal byte is 1° Celsius.
processor. The thermal sensor is composed of control logic, SMBus interface logic, precision
analog-to-digital converters, and precision current sources. The sensor drives a small current
through the p-n junction of a thermal diode located on each processor core. The forward bias
voltage generated across the thermal diode is sensed and the precision A/D converter derives a
single byte of thermal reference data, or a “thermal byte reading.” The nominal precision of the
least significant bit of a thermal byte is 1° Celsius.
The processor incorporates the SMBus thermal sensor onto the processor package consistent with
past members of the Intel Xeon processor family. Upper and lower thermal reference thresholds for
each core can be individually programmed for the SMBus thermal sensor. Comparator circuits
sample the register where the single byte of thermal data for each core (thermal byte reading) is
stored. These circuits compare the single-byte result against programmable threshold bytes. If
enabled, the alert signal on the processor SMBus (SM_ALERT#) will be asserted when the sensor
detects that either core’s threshold is reached or crossed. Analysis of SMBus thermal sensor data
may be useful in detecting changes in the system environment that may require attention. Note that
sensor readings from different cores can vary significantly and must all be monitored.
past members of the Intel Xeon processor family. Upper and lower thermal reference thresholds for
each core can be individually programmed for the SMBus thermal sensor. Comparator circuits
sample the register where the single byte of thermal data for each core (thermal byte reading) is
stored. These circuits compare the single-byte result against programmable threshold bytes. If
enabled, the alert signal on the processor SMBus (SM_ALERT#) will be asserted when the sensor
detects that either core’s threshold is reached or crossed. Analysis of SMBus thermal sensor data
may be useful in detecting changes in the system environment that may require attention. Note that
sensor readings from different cores can vary significantly and must all be monitored.
The SMBus thermal sensor feature in the processor cannot be used to measure T
CASE
. The T
CASE
must be met regardless of the reading of the processor's thermal sensor in
order to ensure adequate cooling for the entire processor. The SMBus thermal sensor feature is only
available while V
available while V
CC
and SM_VCC are at valid levels and the processor is not in a low-power state.
7.4.5
Thermal Sensor Supported SMBus Transactions
The thermal sensor responds to five of the SMBus packet types: Write Byte, Read Byte, Send Byte,
Receive Byte, and Alert Response Address (ARA). The Send Byte packet can be used for sending
one-shot commands. The Receive Byte packet accesses the register commanded by the last Read
Byte packet and can be used to continuously read from a register. If a Receive Byte packet was
preceded by a Write Byte or send Byte packet more recently than a Read Byte packet, then the
behavior is undefined.
Receive Byte, and Alert Response Address (ARA). The Send Byte packet can be used for sending
one-shot commands. The Receive Byte packet accesses the register commanded by the last Read
Byte packet and can be used to continuously read from a register. If a Receive Byte packet was
preceded by a Write Byte or send Byte packet more recently than a Read Byte packet, then the
behavior is undefined.
through
‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘Ack’ represents an acknowledge, and
‘///’ represents a negative acknowledge (NACK). The shaded bits are transmitted by the thermal
sensor, and the bits that aren’t shaded are transmitted by the SMBus host controller.
‘///’ represents a negative acknowledge (NACK). The shaded bits are transmitted by the thermal
sensor, and the bits that aren’t shaded are transmitted by the SMBus host controller.
shows the encoding of the command byte.
Table 7-4. Write Byte SMBus Packet
S
Slave Address
Write
A
Command Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
Table 7-5. Write Byte SMBus Packet
S
Slave Address
Write
Ack
Command Code
Ack
Data
Ack
P
1
7-bits
0
1
8-bits
1
8-bits
1
1