Intel Xeon 7130N LF80550KF0878M Data Sheet

88

Of the addresses broadcast across the SMBus, the memory component claims those of the form 
“1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors on the system 
baseboard. These address pins are pulled down weakly (10 k

Ω) on the processor substrate to ensure 

that the memory components are in a known state in systems which do not support the SMBus (or 
only support a partial implementation). The “Z” bit is the read/write bit for the serial bus 
transaction.

The thermal sensor internally decodes one of three upper address patterns from the bus of the form 
“0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing, as implemented, uses 
the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state. Therefore, the thermal sensor supports 
nine unique addresses. To set either pin for the Hi-Z state, the pin must be left floating. As before, 
the “Z” bit is the read/write bit for the serial transaction.

Note that addresses of the form “0000XXXXb” are Reserved and should not be generated by an 
SMBus master. The thermal sensor samples and latches the SM_TS_A[1:0] signals at power-up 
and at the starting point of every conversion. System designers should ensure that these signals are 
at valid V

IH

, V

IL

, or floating input levels prior to or while the thermal sensor’s SM_VCC supply 

powers up. This should be done by pulling the pins to SM_VCC or V

SS

 via a 1 k

Ω or smaller 

resistor, or leaving the pins floating to achieve the Hi-Z state. If the system designer wants to drive 
the SM_TS_A[1:0] pins with logic, the designer must still ensure that the pins are at valid input 
levels prior to or while the SM_VCC supply ramps up. The system designer must also ensure that 
their particular implementation does not add excessive capacitance to the address inputs. Excess 
capacitance at the address inputs may cause address recognition problems. Refer to the appropriate 
platform design guide document.

 shows a logical diagram of the pin connections. 

 describe the 

address pin connections and how they affect the addressing of the devices.

1. Upper address bits are decoded in conjunction with the device select pins.
2. A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.

System management software must be aware of the processor dependent addresses for the thermal 
sensor.

0

0

0

0

Z

2

1

3Xh

0011000Xb

0011001Xb

0011010Xb

Z

2

Z

2

Z

2

0

Z

2

1

5Xh

0101001Xb

0101010Xb

0101011Xb

1

1

1

0

Z

2

1

9Xh

1001100Xb

1001101Xb

1001110Xb