Intel Xeon 7130N LF80550KF0878M Data Sheet

90

The Header also includes the data format revision at offset 0h and the EEPROM size (formatted in 
hex bytes) at offset 01-02h. The data format revision is used whenever fields within the PIROM are 
redefined. Normally the revision would begin at a value of 1. If a field, or bit assignment within a 
field, is changed such that software needs to discern between the old and new definition, then the 
data format revision field should be incremented.

The EEPROM size provides the size of the PIROM in hex bytes. The PIROM is 128 bytes; thus, 
offset 01 - 02h would be programmed to 80h.

This section contains two pieces of data: 

•

The S-spec/QDF of the part in ASCII format

•

(1) 2-bit field to declare if the part is a pre-production sample or a production unit

The S-spec/QDF field is six ASCII characters wide and is programmed with the same S-spec/QDF 
value as marked on the processor. If the value is less than six characters in length, leading spaces 
(20h) are programmed in this field.

Example: A processor with a QDF mark of QEU5 contains the following in field 0E-13h: 20, 20, 
51, 45, 55, 35h. 

This data consists of two blanks at 0Eh and 0Fh followed by the ASCII codes for QEU5 in 
locations 10 - 13h.

Offset 14h contains the sample/production field, which is a two-bit field and is LSB aligned. All 
Q-spec material will use a value of 00b. All S-spec material will use a value of 01b. All other 
values are reserved.

Example: A processor with a Qxxx mark (engineering sample) will have offset 14h set to 00b. A 
processor with an Sxxxx mark (production unit) will use 01b at offset 14h.

This section contains core silicon-related data.

The CPUID field is a copy of the results in EAX[13:0] from Function 1 of the CPUID instruction. 

The field is not aligned on a byte boundary since the first two bits of the offset are reserved. Thus, 
the data must be shifted right by two in order to obtain the same results.

Example: The CPUID of a C-1 stepping Intel Xeon processor with 512 KB L2 cache is 0F27h. 
The value programmed into offset 16 - 17h of the PIROM is 3C9Ch. 

The first two bits of the PIROM are reserved, as highlighted in the example below.

CPUID instruction results

0000 1111 0010 0111 (0F27h)

PIROM content

0011 1100 1001 1100 (3C9Ch)