Intel X3450 BV80605001911AQ User Manual
Product codes
BV80605001911AQ
Datasheet, Volume 1
25
Interfaces
2.2
PCI Express* Interface
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
PCI Express Base Specification for details of PCI Express.
The number of PCI Express controllers available is dependent on the platform:
• Intel Xeon processor 3400 series with the Intel 3450 Chipset: 1 x16 PCI Express
Graphics or 2x8 PCI Express Graphics are supported.
• Intel Xeon processor 3400 series with Intel 3400 and 3420 Chipset: 1 x16 PCI
Express I/O, 2 x8 PCI Express I/O, or 4 x4 PCI Express I/O are supported.
2.2.1
PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-
and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction which provides a 250-MB/s communications channel in each
direction (500 MB/s total). That is close to twice the data rate of classic PCI. The fact
that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The PCI Express ports support 5.0 GT/s speed as well. Operating at
5.0 GT/s results in twice as much bandwidth per lane as compared to 2.5 GT/s
operation. When operating with more than one PCI Express controller, each controller
can be operating at either 2.5 GT/s or 5.0 GT/s.
and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction which provides a 250-MB/s communications channel in each
direction (500 MB/s total). That is close to twice the data rate of classic PCI. The fact
that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The PCI Express ports support 5.0 GT/s speed as well. Operating at
5.0 GT/s results in twice as much bandwidth per lane as compared to 2.5 GT/s
operation. When operating with more than one PCI Express controller, each controller
can be operating at either 2.5 GT/s or 5.0 GT/s.
The PCI Express architecture is specified in three layers: Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to
for the PCI Express Layering Diagram.
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side the reverse process occurs and
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side the reverse process occurs and
Figure 2-3. PCI Express* Layering Diagram