Intel Celeron 440 HH80557RG041512 Data Sheet
Product codes
HH80557RG041512
Electrical Specifications
28
Datasheet
2.8
Clock Specifications
2.8.1
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to
for the processor supported
ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative. Platforms using a CK505
Clock Synthhesizer/Driver should comply with the specifications in
Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications
in
NOTES:
1.
1.
Individual processors operate only at or below the rated frequency.
2.
Listed frequencies are not necessarily committed production frequencies.
Table 15.
Core Frequency to FSB Multiplier Configuration
Multiplication of System
Core Frequency to FSB
Frequency
Core Frequency
(200 MHz BCLK/800 MHz
FSB)
Notes
1, 2
1/6
1.20 GHz
-
1/7
1.40 GHz
-
1/8
1.60 GHz
-
1/9
1.80 GHz
-
1/10
2 GHz
-
1/11
2.2 GHz
-
1/12
2.4 GHz
-
1/13
2.6 GHz
-
1/14
2.8 GHz
-