Intel QX6700 HH80562PH0678M User Manual

Product codes

HH80562PH0678M

Datasheet

Electrical Specifications

NOTE:
1.

supplies the PECI interface. PECI behavior does not affect V

min/max specifications.

Refer to

Table 4

for V

specifications.

The leakage specification applies to powered devices on the PECI bus.

The input buffers use a Schmitt-triggered input design for improved noise immunity.

Table 12.

CMOS Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

NOTES:

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Input Low Voltage

-0.10

* 0.30

2, 3

is defined as the voltage range at a receiving agent that will be interpreted as a logical low

value.

The V

referred to in these specifications refers to instantaneous V

Input High Voltage

* 0.70

+ 0.10

, 4, 5

is defined as the voltage range at a receiving agent that will be interpreted as a logical high

value.

and V

may experience excursions above V

Output Low Voltage

-0.10

* 0.10

Output High Voltage

0.90 * V

+ 0.10

All outputs are open drain.

Output Low Current

1.70

4.70

, 7

is measured at 0.10 * V

TT.

is measured at 0.90 * V

TT.

Output High Current

1.70

4.70

Input Leakage Current

N/A

± 100

µA

Leakage to V

with land held at V

Output Leakage Current

N/A

± 100

µA

Leakage to V

with land held at 300 mV

Table 13.

PECI DC Electrical Limits

Symbol

Definition and Conditions

Min

Max

Units

Notes

Input Voltage Range

-0.30

hysteresis

Hysteresis

0.1 * V

—

Negative-edge threshold voltage

0.275 * V

0.500 * V

Positive-edge threshold voltage

0.550 * V

0.725 * V

source

High level output source
(V

= 0.75 * V

)

-6.0

N/A

sink

Low level output sink
(V

= 0.25 * V

)

0.5

1.0

leak+

High impedance state leakage to V

N/A

µA

leak-

High impedance leakage to GND

N/A

µA

bus

Bus capacitance

—

noise

Signal noise immunity above 300 MHz

0.1 * V

—

p-p