Intel QX6700 HH80562PH0678M User Manual

Datasheet

29

1.

Unless otherwise noted, all specifications in this table apply to all processor core frequencies

based on a 333 MHz BCLK[1:0].

BCLK[1:0] Frequency

331.635

—

333.364

MHz

-

2

2.

Duty Cycle (High time/Period) must be between 40 and 60%.

T1: BCLK[1:0] Period

2.99972

—

3.01536

ns

3

3.

The period specified here is the average period. A given period may vary from this specification

as governed by the period stability specification (T2). Min period specification is based on -300

PPM deviation from a 3 ns period. Max period specification is based on the summation of +300

PPM deviation from a 3 ns period and a +0.5% maximum variance due to spread spectrum

clocking.

T2: BCLK[1:0] Period Stability

—

—

150

ps

4, 5

4.

For the clock jitter specification, refer to the CK505 Clock Synthesizer/Driver Specification.

5.

In this context, period stability is defined as the worst case timing difference between successive

crossover voltages. In other words, the largest absolute difference between adjacent clock

periods must be less than the period stability.

T5: BCLK[1:0] Rise and Fall Slew Rate

2.5

—

8

V/nS

6

6.

Measurement taken from differential waveform.

T6: Slew Rate Matching

N/A

N/A

20

%

7

7.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured

using a ±75 mV window centered on the average cross point where Clock rising meets Clock#

falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to

use for the edge rate calculations. Slew rate matching is a single ended measurement.

High Time

Period

V

CROSS

CLK 1

CLK 0

Low Time

V

CROSS

 Min

300 mV

V

CROSS

 Max 

500 mV

median

V

CROSS

median

V

CROSS

Median + 75 mV

Median - 75 mV

V

CROSS