Intel 9110N NE80567KE025003 User Manual

25

dI

CC_CACHE

/dt

Slew rate for cache at Ararat output

125

A/us

I

CC_IO

I

CC

 for processor I/O

22

A

7

I

CC_Analog

I

CC

 for processor Analog

6

A

I

CC33_SM

I

CC33

 for main supply

200

mA

1. I

CC_CORE_TDC

 is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be

used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its

temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor

and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see

the Ararat Voltage Regulator Design Guide for further details. The processor is capable of drawing I

CC_CORE_TDC

 indefinitely. Refer

 for further details on the average processor current draw over various time durations. This parameter is based on

design characterization and is not tested.

2. During system power on, the pulse inrush (I

CC_CORE_STEP

)

 

can be as high as 130A peak-to-peak.

3. I

CC_UNCORE_TDC

 is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely and should

be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its

temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor

and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see

the Ararat Voltage Regulator Design Guide for further details. The processor is capable of drawing I

CC_UNCORE_TDC

 indefinitely.

This parameter is based on design characterization and is not tested.

4. During system power on, the pulse inrush (I

CC_UNCORE_STEP

)

 

can be as high as 40A peak-to-peak.

5. I

CC_CACHE_TDC

 is the sustained (DC equivalent) current that the processor cache is capable of drawing indefinitely and should be

used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its

temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor

and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see

the Ararat Voltage Regulator Design Guide for further details. The processor is capable of drawing I

CC_CACHE_TDC

 indefinitely.

This parameter is based on design characterization and is not tested.

6. During system power on, the pulse inrush (I

CC_CACHE_STEP

)

 

can be as high as 40A peak-to-peak.

7. The I

CC_IO

 current specification applies to the total current from VCCIO and VCCIO_FBD pins.

I

CC_CORE

I

CC 

for core

180

A

I

CC_CORE_TDC

Thermal Design Current for Core

131

A

1

1. I

CC_CORE_TDC

 is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be

used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its

temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor

and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see

the Ararat Voltage Regulator Design Guide for further details. The processor is capable of drawing I

CC_CORE_TDC

 indefinitely. Refer

 for further details on the average processor current draw over various time durations. This parameter is based on

design characterization and is not tested.

I

CC_CORE_STEP

Max Load step for core

95

A

2

dI

CC_CORE

/dt

Slew rate for core at Ararat output

154

A/us

I

CC_UNCORE

I

CC

for uncore

50

A

I

CC_UNCORE_TDC

Thermal Design Current for Uncore

43

A

3

I

CC_UNCORE_STEP

Max Load step for uncore

22

A

4

dI

CC_UNCORE

/dt

Slew rate for uncore at Ararat output

75

A/us

I

CC_CACHE

I

CC

 for processor cache

50

A

I

CC_CACHE_TDC

Thermal Design Current for Cache

50

A

5

I

CC_CACHE_STEP

Max Load step for cache

25

A

6

dI

CC_CACHE

/dt

Slew rate for cache at Ararat output

125

A/us

I

CC_IO

I

CC

 for processor I/O

22

A

7

I

CC_Analog

I

CC

 for processor Analog

6

A

I

CC33_SM

I

CC33

 for main supply

200

mA