Intel 9110N NE80567KE025003 User Manual

Product codes
NE80567KE025003
Page of 120
Intel
®
 Itanium
® 
Processor 9300 Series Datasheet
27
Electrical Specifications
2.6.2.2
Cache Static and Transient Tolerances
 specify static and transient tolerances for the uncore 
outputs.
40
VID - 0.16
VID - 0.18
VID - 0.2
45
VID - 0.18
VID - 0.2
VID - 0.22
50
VID - 0.2
VID - 0.22
VID - 0.24
Notes:
1.
The V
CC_MIN
 and V
CC_MAX
 load lines represent static and transient limits.
2.
This table is intended to aid in reading discrete points on 
.
3.
The load lines specify voltage limits at the die measured at the V
CCUNCORESENSE
 and V
SSUNCORESENSE
 pins. 
Voltage regulation feedback for voltage regulator circuits must be taken from processor V
CC
 and V
SS
 pins. 
Refer to the Ararat Voltage Regulator Design Guide for socket load line guidelines and VR implementation.
4.
V
DC
(max)=VID-R
ll
*I
CC
-5mV; V
DC
(min)=VID-R
ll
*I
CC
-35mV; R
ll
=4m
Figure 2-10. VccUNCORE Static and Transient Tolerance
Table 2-11.  V
CCUNCORE
 Static and Transient Tolerance (Sheet 2 of 2)
Uncore 
Current (A)
Voltage Deviation from VID Setting (V)1,2,3,4
VccUNCORE Tolerance Bands
-0.24
-0.22
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0
5
10
15
20
25
30
35
40
45
50
Icc (A)
N
o
rm
al
iz
ed
 V
cc (
V
)
AC max (V)
DC max (V)
Typical Vcc (V)
DC min (V)
AC min (V)