Intel 9150N NE80567KE025015 User Manual

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Offset 3Ch-3Eh provides minimum “operating” memory transfer rate. 

Offset 3Fh-40h is the nominal processor Uncore voltage for this part, rounded to the 
next thousandthin mV and reflected in BCD.

Example: 1200 mV is stored as 3Fh: 00, 40h: 12h.

Offset 41h and 42h contain the Uncore voltage tolerances, high and low respectively. 
These use a decimal to hexadecimal conversion. Example: 20 mV tolerance would be 
saved as 14h.

This section contains cache related data.

Offset 46h-47h is the L3 cache size field. The field reflects the size of the level three 
cache in MBytes in bcd format.

Example: The Intel Itanium processor 9300 series has a 24 MB L3 cache. Thus, offsets 
46h & 47h will contain 24 & 00 respectively.

Offset 48h-49h is the nominal processor cache voltage for this part, rounded to the 
next thousandth in mV and reflected in BCD.

Offset 4Ah and 4Bh contain the cache voltage tolerances, high and low respectively. 
These use a decimal to hexadecimal conversion. Example: 20 mV tolerance would be 
saved as 14h.

This section describes the package revision location at offset 4Fh-53h used to capture 
package technology. This field tracks the highest level revision. It is provided in ASCII 
hex format of five characters.

This field is at offset 54h for the substrate layout design.

This section between 56h and 6Ah provides part tracing ability.