Intel 9150N NE80567KE025015 User Manual

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Offset 72h-75h contains a copy of results in EDX[31:0] from Function 1 of the CPUID 
instruction. These details provide instruction and feature support by product family.

Offset 78h-79h provides additional feature information from the processor. This field is 
defined as follows:

At offset 7Bh, a 4-bit hex digit is used to tell how many devices are in the TAP Chain. 
The four bits are the most significant bits at this offset.

Since Intel Itanium processor 9300 series has one TAP per core plus a sysint TAP, this 
field would be set to 50h. Note that even reduced core count Itanium products (for 
example, 2-core Itanium products) will still have five devices on the TAP chain. 

Addresses 7Dh-7Fh are listed as reserved.

The Processor Information section of the ROM includes multiple checksums. 

includes the checksum values for each section defined in the 128 byte PIROM section, 
except the Other Data section.

4-32

Reserved

3

Thermal calibration offset byte present

2

Scratch (OEM) EEPROM present (set if there is a scratch ROM at offset 80 - FFh)

1

Core VID present (set if there is a VID provided by the processor)

0

Reserved

General

0Eh

Processor Data 

21h

Processor Core Data

2Dh

Processor Uncore Data

45h

Cache Data

4Eh

Package Data

55h

Part Number Data 

6Ah

Thermal Reference Data

71h

Feature Data

7Ch

Other Data

None Defined