Intel 9150N NE80567KE025015 User Manual
Product codes
NE80567KE025015
Intel
®
Itanium
®
Processor 9300 Series Datasheet
17
Electrical Specifications
7.
Defined as the total variation of all crossing voltages of Rising SYSCLK and falling SYSCLK_N. This is the maximum allowed
.
8.
9.
Defined as the minimum instantaneous voltage including undershoot. See
.
10. T
Stable
is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges
before it is allowed to droop back into the VRB ±100 mV range. See
.
11. See Referenced Clock Jitter Tool in Section 1.2.
2.4
Intel QuickPath Interconnect and Intel SMI
Signaling Specifications
.
2.4.1
Intel QuickPath Interconnect and Intel SMI Specifications
for 4.8 GT/s
This section contains information for QPI slow boot up speed (1/4 frequency of the
reference clock) and processor’s normal operating frequency, 4.8 GT/s, for Intel QPI
and Intel SMI.
reference clock) and processor’s normal operating frequency, 4.8 GT/s, for Intel QPI
and Intel SMI.
For Intel QPI slow boot up speed, the signaling rate is defined as 1/4 the rate of the
system reference clock. For example, a 133 MHz system reference clock would have a
forwarded clock frequency of 33.33 MHz and the signaling rate would be 66.67 MT/s.
system reference clock. For example, a 133 MHz system reference clock would have a
forwarded clock frequency of 33.33 MHz and the signaling rate would be 66.67 MT/s.
The transfer rates available for the processor are shown in
. Transmitter and
receiver parameters for Intel QPI slow mode, Intel QPI and Intel SMI are shown in
Table 2-4.
Clock Frequency Table
Intel
®
QuickPath Interconnect
Forwarded Clock Frequency
Intel
®
QuickPath Interconnect Data
Transfer Rate
33.33 MHz
66.66 MT/s (see note 1
)
Notes:
1. This speed is the 1/4 SysClk Frequency.
2.40 GHz
4.8 GT/s
Table 2-5.
Transmitter Parameter Values for Intel QuickPath Interconnect and
Intel SMI Channels @ 4.8 GT/s (Sheet 1 of 2)
Symbol
Parameter
Min
Nom
Max
Units
Notes
UI
avg
Average UI size at 4.8 GT/s
208.33
ps
N
MIN-UI-Validation
# of UI over which the eye mask voltage and
timing spec needs to be validated
1E6
T
slew-rise-fall-pin
Defined as the slope of the rising or falling
waveform as measured between +/-100 mV
of the differential transmitter output, data or
clock
6
12
V/ns
V
Tx-diff-pp-pin
Transmitter differential swing
900
1300
mV
R
TX
Transmitter termination resistance
37.4
47.6
4
Z
TX_LINK_DETECT
Link Detection Resistor
500
2000
V
TX_LINK_DETECT
Link Detection Resistor Pull-up Voltage
max VCCIO
V
T
DATA_TERM_SKEW
Intel QPI
Skew between first to last data termination
meeting Z
RX_LOW_CM_DC
600
UI
2
T
DATA_TERM_SKEW
Intel SMI
Skew between first to last data termination
meeting Z
RX_LOW_CM_DC
780
UI
2