Intel 9150N NE80567KE025015 User Manual

16

The processor has one input reference clock, SYSCLK/SYSCLK_N for the Intel QPI 
interface. The processor timing specified in this section is defined at the processor pins 
unless otherwise noted. 

1.

Measurement taken from single-ended waveform.

2.

The given PLL parameters are: Underdamping (z) = 0.8 and natural frequency = fn = 7.86E6 Hz; wn = 2 *fn. N_minUI = 12 

for Intel

®

 QuickPath Interconnect 4.8 Gt/s channel.

3.

Measurement taken from differential waveform.

4.

Measured from -150 mV to +150 mV on the differential waveform (derived from SYSCLK minus SYSCLK_N). The signal must 

be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the 

differential zero crossing. See 

5.

Measured at crossing point where the instantaneous voltage value of the rising edge SYSCLK equals the falling edge 

SYSCLK_N. See 

.

6.

Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all 

crossing points for this measurement. See 

.

PIROM

Input

PIR_SCL

I/O

PIR_SDA

Input

PIR_A0

Input

PIR_A1

Input

SM_WP

1. CMOS signals have a reference voltage (Vref) equal to VCCIO/2.

2. GTL signals have a reference voltage (Vref) equal to VCCIO*(2/3).

3. These signals are connected to the Ararat voltage regulator from the topside of the processor.

fsysclk (ssc-off)

System clock frequency

133.31

133.33

133.34

MHz

Fsyclk (scc-on)

System clock frequency

132.62

132.99

133.37

MHz

ER

sysclk-diff-Rise,

ER

sysclk-diff-Fall

Differential Rising and Falling Edge 

Rates

1.0

4.0

V/ns

3,4

T

sysclk_dutycycle

Duty cycle of Reference clock

40

60

% period

3

C

i-CK

Clock Input Capacitance

0.5

2.0

pf

VH

Differential High Input Voltage

0.15

V

3

VL

Differential Low Input Voltage

-0.15

V

3

V

Cross

Absolute crossing point 

0.25

0.35

0.55

V

1,5,6

V

Cross_delta

Peak-peak variation 

140

mv

1,5,7

V

max Overshoot

Single-ended maximum voltage

1.54

V

1,8

V

min Undershoot

Single-ended minimum voltage

-0.337

V

1,9

V

RB-Diff

Differential Ringback voltage 

threshold

-100

100

mV

3,10

T

Stable

Allowed time before ringback

500

ps

3,10

T

REFCLK

-

JITTER

-

RMS

-

ONEPLL

Accumulated rms jitter over n UI of a 

given PLL model output in response to 

the jittery reference clock input. The 

PLL output is generated by convolving 

the measured reference clock phase 

jitter with a given PLL transfer 

function. Here n=12.

0.5

ps

2,11