Intel X3470 BV80605001905AJ User Manual
Product codes
BV80605001905AJ
Datasheet, Volume 1
21
Interfaces
2.1.2
System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
command signal mode timings on the main memory interface:
• t
CL
= CAS Latency
• t
RCD
= Activate Command to READ or WRITE Command delay
• t
RP
= PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1N indicates a new command may be issued every clock
• Command Signal modes = 1N indicates a new command may be issued every clock
and 2N indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
mode programming depends on the transfer rate and memory configuration.
Note:
1.
Two Un-buffered DIMM Memory Configurations = 2N Command Mode at 1067/1333 MHz
2.
One Un-buffered DIMM Memory Configurations = 1N Command Mode at 1067/1333 MHz
3.
Both Channel A and B will run at same Command Mode based on the slowest mode enabled relative to the
memory configurations populated in both channels. For example, if Channel A has both DIMM connectors
populated (2N CMD Mode) and Channel B has only one DIMM connector populated (1N CMD Mode) then 2N
CMD mode would be enabled for both channels.
4.
System Memory timing support is based on availability and is subject to change.
2.1.3
System Memory Organization Modes
The IMC supports two memory organization modes, single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated, but not
both.
is used when either Channel A or Channel B DIMM connectors are populated, but not
both.
Table 2-2.
DDR3 System Memory Timing Support
Transfer
Rate
(MT/s)
t
CL
(t
CK
)
t
RCD
(t
CK
)
t
RP
(t
CK
)
CWL
(t
CK
)
Unbuffered
DIMM CMD
Mode
Registered
DIMM CMD
Mode
Notes
6
6
6
5
N/A
1N Only
4
1066
7
7
7
6
See Note 1, 2, 3
1N Only
4
8
8
8
1333
8
8
8
7
See Note 1, 2, 3
1N Only
4
9
9
9
4
10
10
10
4