Intel X3470 BV80605001905AJ User Manual
Product codes
BV80605001905AJ
Datasheet, Volume 1
23
Interfaces
2.1.3.2.2
Dual-Channel Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start at the bottom of Channel A and stay there until the end of the highest
rank in Channel A, and then addresses continue from the bottom of Channel B to the
top. Real world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization, so in most
cases, bandwidth is limited to a single channel.
addresses start at the bottom of Channel A and stay there until the end of the highest
rank in Channel A, and then addresses continue from the bottom of Channel B to the
top. Real world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization, so in most
cases, bandwidth is limited to a single channel.
This mode is used when Intel Flex Memory Technology is disabled and both Channel A
and Channel B DIMM connectors are populated in any order with the total amount of
memory in each channel being different.
and Channel B DIMM connectors are populated in any order with the total amount of
memory in each channel being different.
2.1.4
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports one or two DIMM
connectors per channel for unbuffered DIMMs or up to three DIMM connectors per
channel for registered DIMMs.For dual-channel modes, both channels must have at
least one DIMM connector populated and for single-channel mode only a single-channel
may have one or more DIMM connectors populated.
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports one or two DIMM
connectors per channel for unbuffered DIMMs or up to three DIMM connectors per
channel for registered DIMMs.For dual-channel modes, both channels must have at
least one DIMM connector populated and for single-channel mode only a single-channel
may have one or more DIMM connectors populated.
Note:
DIMM0 must always be populated within any memory configuration. DIMM0 is the
furthest DIMM within a channel and is identified by the CS#[1:0], ODT[1:0], and
CKE[1:0] signals.
Figure 2-2. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
CH. B
CH. A
CH. B
CH. A
CH. B
CH. A
CL
0
Top of
Memory
Memory
CL
0
CH. B
CH. A
CH.A-top
DRB
DRB
Dual Channel Interleaved
(memory sizes must match)
Dual Channel Asymmetric
(memory sizes can differ)
Top of
Memory
Memory