Intel 2 Duo T5600 LE80537GF0342M User Manual

Datasheet

11

The Intel Core 2 Duo mobile processor supports low power states both at the individual 

core level and the package level for optimal power management. A core may 

independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states. 

Refer to

 for a visual representation of the core low power states for the 

processor. When both cores coincide in a common core low power state, the central 

power management logic ensures the entire Intel Core 2 Duo mobile processor enters 

the respective package low power state by initiating a P_LVLx (P_LVL2, P_LVL3, and 

P_LVL4) I/O read to the Intel 945GM/GT/GMS/PM and 940GML Express Chipset family. 

Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep, Deep 

Sleep, and Deeper Sleep.

 

Refer to 

 for a visual representation of the package 

low power states for the Intel Core 2 Duo mobile processor and to 

 for a 

mapping of core low power states to package low power states.

The Intel Core 2 Duo mobile processor implements two software interfaces for 

requesting low power states: MWAIT instruction extensions with sub-state hints and 

P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address 

space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests 

inside the processor and do not directly result in I/O reads on the processor FSB. The 

monitor address does not need to be setup before using the P_LVLx I/O read interface. 

The sub-state hints used for each P_LVLx read can be configured through a software 

programmable Model Specific Register (MSR).

If a core encounters a chipset break event while STPCLK# is asserted, then it asserts 

the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to 

system logic that individual cores should return to the C0 state and the Intel Core 2 

Duo mobile processor should return to the Normal state.