Intel 2 Duo T5600 LE80537GF0342M User Manual
Product codes
LE80537GF0342M
Datasheet
13
Low Power Features
2.1.1
Core Low Power State Descriptions
2.1.1.1
Core C0 State
This is the normal operating state for cores in the processor.
2.1.1.2
Core C1/AutoHALT Powerdown State
C1/AutoHALT is a low power state entered when a core executes the HALT instruction.
The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,
LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to
immediately initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Intel®
Architectures Software Developer's Manual, Volume 3A/3B: System Programmer's
Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
will return execution to the HALT state.
Figure 2.
Package Low Power States
Table 1.
Coordination of Core Low Power States at the Package Level
Package State
Core1 State
Core0 State
C0
C1/Auto
HALT/
MWAIT
C2
C3
C4
C0
Normal
Normal
Normal
Normal
Normal
C1/AutoHALT/
MWAIT
Normal
Normal
Normal
Normal
Normal
C2
Normal
Normal
Stop-Grant
Stop-Grant
Stop-Grant
C3
Normal
Normal
Stop-Grant
Deep Sleep
Deep Sleep
C4
Normal
Normal
Stop-Grant
Deep Sleep
Deeper Sleep/
Intel®
Enhanced
Deeper Sleep
Stop
Grant
Snoop
Normal
Stop
Grant
Deep
Sleep
STPCLK# asserted
Snoop
serviced
Snoop
occurs
occurs
Deeper
Sleep
†
Sleep
SLP# asserted
SLP# de-asserted
DPSLP# asserted
DPSLP# de-asserted
DPRSTP# de-asserted
DPRSTP# asserted
STPCLK# de-asserted
† — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state.