Intel LF80550KF100007 Data Sheet

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

21

3.

f

peak

, if existent, should be less than 0.05 MHz.

4.

f

core

 represents the maximum core frequency supported by the platform.

The VID[5:0] pins supply the encodings that determine the voltage to be supplied by 
the V

CC

 (the core voltage for the Dual-Core Intel Xeon processor 7100 series) voltage 

regulator. The VID specification for the Dual-Core Intel Xeon processor 7100 series is 
defined by the Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator 
Down (EVRD) 10.2 Design Guidelines. The voltage set by the VID signals is the 
maximum V

CC

 voltage allowed by the processor. VID signals are open drain outputs, 

which must be pulled up to V

TT

. Please refer to 

 for the DC specifications for 

these signals. A minimum V

CC 

voltage is provided in 

 and changes with 

frequency. This allows processors running at a higher frequency to have a relaxed 
minimum V

CC 

voltage specification. The specifications have been set such that one 

voltage regulator can work with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two 
devices at the same core speed may have different default VID settings. Furthermore, 
any Dual-Core Intel® Xeon® Processor 7100 Series processor, even those on the same 
processor front side bus, can drive different VID settings during normal operation.

The Dual-Core Intel Xeon processor 7100 series uses six voltage identification pins, 
VID[5:0], to support automatic selection of power supply voltages. 

the voltage level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a 
high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is 
empty (i.e. VID[5:0] = x11111), or the voltage regulation circuit cannot supply the 
voltage that is requested, the processor’s voltage regulator must disable itself. See the 
Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 
10.2 Design Guidelines for more details.

The Dual-Core Intel Xeon processor 7100 series provides the ability to operate while 
transitioning to an adjacent VID and its associated processor core voltage (V

CC

). This 

will represent a DC shift in the load line. It should be noted that a low-to-high or high-
to-low voltage state change may result in as many VID transitions as necessary to 
reach the target core voltage. Transitions above the specified VID are not permitted. 

 includes VID step sizes and DC shift ranges. Minimum and maximum 

voltages must be maintained as shown in 

 and 

The VRM or VRD utilized must be capable of regulating its output to the value defined 
by the new VID. DC specifications for VID transitions are included in 

. Please refer to the Vcc Voltage Regulator Module (VRM) and Enterprise 

Voltage Regulator-Down (EVRD) 10.2 Design Guidelines for further details.

Power source characteristics must be guaranteed to be stable whenever the supply to 
the voltage regulator is stable.