Intel LF80550KF100007 Data Sheet
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
23
Electrical Specifications
series is defined by the VRM 9.1 DC-DC Converter Design Guidelines. The voltage set
by the CVID pins is the maximum V
by the CVID pins is the maximum V
CACHE
voltage allowed by the processor. A minimum
V
CACHE
voltage is provided in
.
Dual-Core Intel Xeon processor 7100 series with the same front side bus frequency,
internal cache sizes, and stepping will have consistent CVID values.
internal cache sizes, and stepping will have consistent CVID values.
The Dual-Core Intel Xeon processor 7100 series uses four voltage identification pins
(CVID[3:0]) to support automatic selection of power supply voltages.
(CVID[3:0]) to support automatic selection of power supply voltages.
specifies the voltage level corresponding to the state of CVID[3:0]. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor
socket is empty (in a single processor per regulator design), or if both processor
sockets are empty (in a two processors per regulator design), or the voltage regulation
circuit cannot supply the voltage that is requested, the processor’s voltage regulator
must disable itself. See the VRM 9.1 DC-DC Converter Design Guidelines for more
details.
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor
socket is empty (in a single processor per regulator design), or if both processor
sockets are empty (in a two processors per regulator design), or the voltage regulation
circuit cannot supply the voltage that is requested, the processor’s voltage regulator
must disable itself. See the VRM 9.1 DC-DC Converter Design Guidelines for more
details.
Note:
The voltage regulator will have a fifth VID input and, for VRM 10.2-compliant regulators, a sixth VID
input as well. The extra input(s) should be tied to a high voltage on the motherboard for correct
operation. Refer to the appropriate platform design guide for further implementation details.
2.4
Reserved, Unused, and TESTHI Pins
All RESERVED pins must be left unconnected. Connection of these pins to V
CC
, V
SS
, or
to any other signal (including each other) can result in component malfunction or
incompatibility with future processors. See
incompatibility with future processors. See
Section 5
for a pin listing for the processor
and the location of all RESERVED pins.
For reliable operation, always terminate unused inputs or bidirectional signals to their
respective deasserted states. On-die termination has been included on the Dual-Core
Intel Xeon processor 7100 series to allow signals to be terminated within the processor
respective deasserted states. On-die termination has been included on the Dual-Core
Intel Xeon processor 7100 series to allow signals to be terminated within the processor
Table 2-5.
Cache Voltage Identification (CVID) Definition
CVID3
CVID2
CVID1
CVID0
CVID (V)
1
1
1
1
Off
1
1
1
0
1.100
1
1
0
1
1.125
1
1
0
0
1.150
1
0
1
1
1.175
1
0
1
0
1.200
1
0
0
1
1.225
1
0
0
0
1.250
0
1
1
1
1.275
0
1
1
0
1.300
0
1
0
1
1.325
0
1
0
0
1.350
0
0
1
1
1.375
0
0
1
0
1.400
0
0
0
1
1.425
0
0
0
0
1.450