Intel LF80550KF100007 Data Sheet
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
83
Features
7
Features
7.1
Power-On Configuration Options
Several configuration options can be set by hardware. The Dual-Core Intel Xeon
processor 7100 series samples its hardware configuration at reset, on the active-to-
inactive transition of RESET#. For specifications on these options, refer to
processor 7100 series samples its hardware configuration at reset, on the active-to-
inactive transition of RESET#. For specifications on these options, refer to
The sampled information configures the processor for subsequent operation. These
configuration options can only be changed by another reset. All resets configure the
processor. For reset purposes, the processor does not distinguish between a “warm”
reset and a “power-on” reset.
configuration options can only be changed by another reset. All resets configure the
processor. For reset purposes, the processor does not distinguish between a “warm”
reset and a “power-on” reset.
Note:
1.
Asserting this signal during RESET# selects the corresponding option.
2.
Address pins not identified in this table as configuration options should not be asserted during RESET#.
7.2
Clock Control and Low Power States
The processor allows the use of HALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See
power states.
The Dual-Core Intel Xeon processor 7100 series adds support for Enhanced HALT power
down state. Refer to
down state. Refer to
and the following sections. For more configuration
details, also refer to the Cedar Mill Processor Family BIOS Writer’s Guide.
The Stop-Grant state requires chipset and BIOS support on multiprocessor systems. In
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. The Hyper-Threading Technology feature adds the
conditions that all logical processors share the same STPCLK# signal internally. When
the STPCLK# signal is asserted, the processor enters the Stop-Grant state, issuing a
Stop-Grant Special Bus Cycle (SBC) for each processor or logical processor. The chipset
needs to account for a variable number of processors asserting the Stop-Grant SBC on
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. The Hyper-Threading Technology feature adds the
conditions that all logical processors share the same STPCLK# signal internally. When
the STPCLK# signal is asserted, the processor enters the Stop-Grant state, issuing a
Stop-Grant Special Bus Cycle (SBC) for each processor or logical processor. The chipset
needs to account for a variable number of processors asserting the Stop-Grant SBC on
Table 7-1.
Power-On Configuration Option Pins
Configuration Option
Pin
1,2
Output tri state
SMI#
or
A[39]# for Arb ID 3 (middle agent)
A[36]# for Arb ID 0 (end agent)
Execute BIST (Built-In Self Test)
INIT# or A[3]#
In Order Queue de-pipelining (set IOQ depth to 1)
A[7]#
Disable MCERR# observation
A[9]#
Disable BINIT# observation
A[10]#
APIC cluster ID
A[12:11]#
Disable bus parking
A[15]#
Core Frequency-to-Front Side Bus Multiplier
A[21:16]#
Symmetric agent arbitration ID
BR[1:0]#
Disable Hyper-Threading Technology (HT Technology)
A[31]#