Intel LF80550KF100007 Data Sheet
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
85
Features
7.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20
bus clocks after the response phase of the processor-issued Stop Grant Acknowledge
special bus cycle. For the Dual-Core Intel Xeon processor 7100 series, both logical
processors must be in the Stop-Grant state before the deassertion of STPCLK#.
bus clocks after the response phase of the processor-issued Stop Grant Acknowledge
special bus cycle. For the Dual-Core Intel Xeon processor 7100 series, both logical
processors must be in the Stop-Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should
not be driven (allowing the level to return to V
not be driven (allowing the level to return to V
TT
) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the front side bus
should be driven to the inactive state.
should be driven to the inactive state.
BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched
and can be serviced by software upon exit from the Stop-Grant state.
and can be serviced by software upon exit from the Stop-Grant state.
RESET# causes the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. A transition back to the Normal state occurs with the deassertion
of the STPCLK# signal.
in Stop-Grant state. A transition back to the Normal state occurs with the deassertion
of the STPCLK# signal.
A transition to the Grant Snoop state occurs when the processor detects a snoop on the
front side bus (see
front side bus (see
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] are latched by the
processor, and only serviced when the processor returns to the Normal state. Only one
occurrence of each event is recognized upon return to the Normal state.
processor, and only serviced when the processor returns to the Normal state. Only one
occurrence of each event is recognized upon return to the Normal state.
Figure 7-1. Stop Clock State Machine
Enhanced HALT or HALT State
BCLK running
Snoops and interrupts allowed
Snoops and interrupts allowed
Normal State
Normal execution
Enhanced HALT Snoop or HALT
Snoop State
Snoop State
BCLK running
Service snoops to caches
Service snoops to caches
Stop Grant State
BCLK running
Snoops and interrupts allowed
Snoops and interrupts allowed
Snoop
Event
Occurs
Snoop
Event
Serviced
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
RESET#, FSB interrupts
STPCLK#
Asserted
Asserted
STPCLK#
De-asserted
De-asserted
S
TP
C
LK
#
A
ss
er
te
d
S
TP
C
LK
#
D
e-
as
se
rte
d
Snoop Event Occurs
Snoop Event Serviced
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
HALT Bus Cycle Generated
Stop Grant Snoop State
BCLK running
Service snoops to caches
Service snoops to caches