Intel LF80550KF100007 Data Sheet
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
87
Features
performance and power requirements of the processor and system. Note that the front
side bus is not altered; only the internal core frequency is changed. In order to run at
reduced power consumption, the voltage is altered in step with the bus ratio.
side bus is not altered; only the internal core frequency is changed. In order to run at
reduced power consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep technology:
• Voltage/frequency selection is software controlled by writing to processor MSR’s
(Model Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, V
CC
is incremented
in steps (+12.5 mV) by placing a new value on the VID signals and the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts
to the new frequency and V
CC
is then decremented in steps (-12.5 mV) by
changing the target VID through the VID signals.
Refer to the Cedar Mill Processor Family BIOS Writer’s Guide for specific information to
enable and configure Enhanced Intel SpeedStep technology in BIOS.
enable and configure Enhanced Intel SpeedStep technology in BIOS.
7.4
System Management Bus (SMBus) Interface
The Dual-Core Intel Xeon processor 7100 series package includes an SMBus interface
which allows access to a memory component with two sections (referred to as the
Processor Information ROM and the Scratch EEPROM) and a thermal sensor on the
substrate. The SMBus thermal sensor may be used to read the thermal diode
mentioned in
which allows access to a memory component with two sections (referred to as the
Processor Information ROM and the Scratch EEPROM) and a thermal sensor on the
substrate. The SMBus thermal sensor may be used to read the thermal diode
mentioned in
. These devices and their features are described below.
The SMBus thermal sensor and its associated thermal diode are not related to and are
completely independent of the precision, on-die temperature sensor and thermal
control circuit (TCC) of the Thermal Monitor or Thermal Monitor 2 features discussed in
completely independent of the precision, on-die temperature sensor and thermal
control circuit (TCC) of the Thermal Monitor or Thermal Monitor 2 features discussed in
.
The processor SMBus implementation uses the clock and data signals of the System
Management Bus (SMBus) Specification. It does not implement the SMBSUS# signal.
Layout and routing guidelines are available in the appropriate platform design guide
document.
Management Bus (SMBus) Specification. It does not implement the SMBSUS# signal.
Layout and routing guidelines are available in the appropriate platform design guide
document.
For platforms which do not implement any of the SMBus features found on the
processor, all of the SMBus connections, except SM_VCC, to the socket pins may be
left unconnected (SM_ALERT#, SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0],
SM_WP).
processor, all of the SMBus connections, except SM_VCC, to the socket pins may be
left unconnected (SM_ALERT#, SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0],
SM_WP).