Intel D425 AU80610006252AA User Manual

Datasheet 

 145 

B/D/F/Type: 0/2/1/PCI 

Address Offset: 

54-57h 

Default Value: 

00000019h 

Access:  

RO; 

Size: 32 

bits 

Allows for enabling/disabling of PCI devices and functions that are within the CPU 
Uncore. The table below the bit definitions describes the behavior of all combinations 

of transactions to devices controlled by this register.  

31:15 RO 

00000h  RESERVED ():  

14 RO 

0b  RESERVED () 

 

13:5 RO 

000h  RESERVED ():  

4 RO 

1b 

Internal Graphics Engine Function 1 (D2F1EN):  
0: Bus 0 Device 2 Function 1 is disabled and hidden 
1: Bus 0 Device 2 Function 1 is enabled and visible 
If Device 2 Function 0 is disabled and hidden, then 
Device 2 Function 1 is also disabled and hidden 
independent of the state of this bit. 
If this component is not capable of Dual Independent 
Display (CAPID0[40] = 1) then this bit is hardwired 
to 0b to hide Device 2 Function 1. 

3 RO 

1b 

Internal Graphics Engine Function 0 (D2F0EN):  
0: Bus 0 Device 2 Function 0 is disabled and hidden 
1: Bus 0 Device 2 Function 0 is enabled and visible 
If this CPU Uncore does not have internal graphics 
capability (CAPID0[46] = 1) then Device 2 Function 
0 is disabled and hidden independent of the state of 
this bit. 

2:1 RO 

00b  Reserved ():  

0 RO 

1b 

Host Bridge (D0EN):  
Bus 0 Device 0 Function 0 may not be disabled and 
is therefore hardwired to 1.