Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
146
Datasheet
1.10.20 SSRW - Mirror of Fun 0 Software Scratch Read Write
B/D/F/Type: 0/2/1/PCI
Address Offset:
58-5Bh
Default Value:
00000000h
Access:
RO;
Size: 32
bits
Bit Access Default
Value
Description
31:0 RO
00000000
h
Reserved R/W ():
1.10.21 BSM - Mirror of Func0 Base of Stolen Memory
B/D/F/Type: 0/2/1/PCI
Address Offset:
5C-5Fh
Default Value:
00000000h
Access:
RO;
Size: 32
bits
Graphics Stolen Memory and Tseg are within DRAM space defined under TOLUD. From
the top of low used DRAM, CPU Uncore claims 1 to 64MBs of DRAM for internal
the top of low used DRAM, CPU Uncore claims 1 to 64MBs of DRAM for internal
graphics if enabled.
The base of stolen memory will always be below 4G. This is required to prevent
aliasing between stolen range and the reclaim region.
aliasing between stolen range and the reclaim region.
Bit Access Default
Value
Description
31:20 RO 000h
Base of Stolen Memory (BSM):
This register contains bits 31 to 20 of the base
address of stolen DRAM memory. The host
interface determines the base of Graphics Stolen
memory by subtracting the graphics stolen
memory size from TOLUD. See Device 0 TOLUD
for more explanation.
This register contains bits 31 to 20 of the base
address of stolen DRAM memory. The host
interface determines the base of Graphics Stolen
memory by subtracting the graphics stolen
memory size from TOLUD. See Device 0 TOLUD
for more explanation.
19:0 RO 00000h
Reserved ():