Intel D425 AU80610006252AA User Manual

Datasheet 

 149 

B/D/F/Type: 0/2/1/PCI 

Address Offset: 

D0-D1h 

Default Value: 

0001h 

Access:  

RO; 

Size: 16 

bits 

This register is a mirror of function 0 with the same R/W attributes.  The hardware 
implements a single physical register common to both functions 0 and 1. 

 

 

15:8 RO  00h 

Next Capability Pointer (NEXT_PTR):  
This contains a pointer to next item in 
capabilities list. This is the final capability in 
the list and must be set to 00h. 

7:0 RO  01h 

Capability Identifier (CAP_ID):  
SIG defines this ID is 01h for power 
management. 

B/D/F/Type: 0/2/1/PCI 

Address Offset: 

D2-D3h 

Default Value: 

0022h 

Access:  

RO; 

Size: 16 

bits 

This register is a Mirror of Function 0 with the same read/write attributes. The 
hardware implements a single physical register common to both functions 0 and 1. 

 

 

15:11 RO 

00h 

PME Support (PMES):  
 This field indicates the power states in which 
the IGD may assert PME#. Hardwired to 0 to 
indicate that the IGD does not assert the PME# 
signal. 

10 RO  0b 

D2 Support (D2):  
 The D2 power management state is not 
supported. This bit is hardwired to 0. 
 

9 RO  0b 

D1 Support (D1):  
 Hardwired to 0 to indicate that the D1 power 
management state is not supported. 
 

8:6 RO  000b