Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
150
Datasheet
Bit Access Default
Value
Description
5 RO 1b
Device Specific Initialization (DSI):
Hardwired to 1 to indicate that special
initialization of the IGD is required before
generic class device driver is to use it.
Hardwired to 1 to indicate that special
initialization of the IGD is required before
generic class device driver is to use it.
4 RO 0b
Reserved ():
3 RO 0b
PME Clock (PMECLK):
Hardwired to 0 to indicate IGD does not
support PME# generation.
Hardwired to 0 to indicate IGD does not
support PME# generation.
2:0 RO 010b
Version (VER):
Hardwired to 010b to indicate that there are 4
bytes of power management registers
implemented and that this device complies
with revision 1.1 of the PCI Power
Management Interface Specification.
Hardwired to 010b to indicate that there are 4
bytes of power management registers
implemented and that this device complies
with revision 1.1 of the PCI Power
Management Interface Specification.
1.10.27 PMCS - Power Management Control/Status
B/D/F/Type: 0/2/1/PCI
Address Offset:
Address Offset:
D4-D5h
Default Value:
0000h
Access:
RO; RW;
Size: 16
bits
Bit Access Default
Value
Description
15 RO 0b
PME Status (PMESTS):
This bit is 0 to indicate that IGD does not
support PME# generation from D3 (cold).
This bit is 0 to indicate that IGD does not
support PME# generation from D3 (cold).
14:13 RO
00b
Data Scale (DSCALE):
The IGD does not support data register. This
bit always returns 0 when read, write
operations have no effect.
The IGD does not support data register. This
bit always returns 0 when read, write
operations have no effect.
12:9 RO
0h
Data Select (DATASEL):
The IGD does not support data register. This
bit always returns 0 when read, write
operations have no effect.
The IGD does not support data register. This
bit always returns 0 when read, write
operations have no effect.
8 RO 0b
PME Enable (PME_EN):
This bit is 0 to indicate that PME# assertion
from D3 (cold) is disabled.
This bit is 0 to indicate that PME# assertion
from D3 (cold) is disabled.
7:2 RO 00h
Reserved ():
1:0 RW 00b
Power State (PWRSTAT):
This field indicates the current power state of
the IGD and can be used to set the IGD into a
new power state. If software attempts to write
This field indicates the current power state of
the IGD and can be used to set the IGD into a
new power state. If software attempts to write