Intel D425 AU80610006252AA User Manual

Product codes
AU80610006252AA
Page of 153
 
Processor Configuration Registers 
 
 
 
152  
 
Datasheet  
1.11 
Device 2 IO 
Register 
Name 
Register 
Symbol 
Register 
Start 
Register 
End 
Default 
Value 
Access 
MMIO 
Address 
Register 
Index 0  3  00000000h 
RW; 
MMIO Data 
Register 
Data 4  7 00000000h 
RW; 
1.11.1 
Index - MMIO Address Register 
B/D/F/Type: 0/2/0/PCI 
IO 
Address Offset: 
0-3h 
Default Value: 
00000000h 
Access: RW; 
Size: 32 
bits 
MMIO_INDEX: A 32 bit IO write to this port loads the offset of the MMIO register or 
offset into the GTT that needs to be accessed. An IO Read returns the current value of 
this register. An 8/16 bit IO write to this register is completed by the CPU UNCORE 
but does not update this register. 
This mechanism to access internal graphics MMIO registers must not be used to 
access VGA IO registers which are mapped through the MMIO space. VGA registers 
must be accessed directly through the dedicated VGA IO ports. 
 
 
Bit Access Default 
Value 
Description 
31:2 RW 00000000h 
Register/GTT Offset (REGGTTO):  
This field selects any one of the DWORD 
registers within the MMIO register space 
of Device #2 if the target is MMIO 
Registers. 
This field selects a GTT offset if the 
target is the GTT. 
1:0 RW  00b 
Target (TARG):  
•  00: MMIO Registers 
•  01: GTT 
•  1X: Reserved