Intel D425 AU80610006252AA User Manual

Datasheet 

 25 

translated address hits enabled SMM DRAM space, an error is recorded in the 

PGTBL_ER register.  

DMI Interface originated accesses are never allowed to access SMM space directly or 
through the GTT TLB address translation. If a GTT TLB translated address hits enabled 
SMM DRAM space, an error is recorded in the PGTBL_ER register.  

DMI Interface write accesses through GMADR range will be snooped. Assesses to 
GMADR linear range (defined via fence registers) are supported. DMI Interface tileY 

and tileX writes to GMADR are not supported. If, when translated, the resulting 
physical address is to be enabled SMM DRAM space, the request will be remapped to 

address 000C_0000h with deasserted byte enables.  

DMI Interface read accesses to the GMADR range are not supported therefore will 
have no address translation concerns. DMI Interface reads to GMADR will be 

remapped to address 000C_0000h. The read will complete with UR (unsupported 
request) completion status. 

GTT fetches are always decoded (at fetch time) to ensure not in SMM (actually, 
anything above base of TSEG or 640K-1M). Thus, they will be invalid and go to 

address 000C_0000h, but that isn’t specific to DMI; it applies to CPU or internal 
graphics engines. In addition, since the GMADR snoop would not be directly to the 

SMM space, there wouldn’t be a writeback to SMM. In fact, the writeback would also 

be invalid (because it uses the same translation) and go to address 000C_0000h.. 

Any block of memory that can be designated as read-only or write-only can be 
“shadowed” into IMC DRAM memory. Typically this is done to allow ROM code to 
execute more rapidly out of main DRAM. ROM is used as a read-only during the copy 

process while DRAM at the same time is designated write-only. After copying, the 

DRAM is designated read-only so that ROM is shadowed. CPU bus transactions are 
routed accordingly. 

The processor does not support the existence of any other I/O devices beside itself on 
the CPU bus. The processor generates DMI Interface bus cycles for all CPU I/O 

accesses that it does not claim. Within the host bridge, the processor contains two 
internal registers in the CPU I/O space, Configuration Address Register 

(CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). These 

locations are used to implement configuration space access mechanism.  

The CPU allows 64K+3 bytes to be addressed within the I/O space. The processor 
propagates the CPU I/O address without any translation on to the destination bus and 
therefore provides addressability for 64K+3 byte locations. Note that the upper 3 

locations can be accessed only during I/O address wrap-around when CPU bus HA_16 

address signal is asserted. HA_16 is asserted on the CPU bus whenever an I/O access 
is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HA_16 is also asserted 

when an I/O access is made to 2 bytes from address 0FFFFh.