Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
26
Datasheet
A set of I/O accesses (other than ones used for configuration space access) are
consumed by the internal graphics device if it is enabled. The mechanisms for internal
consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics IO decode and the associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI Interface bus. I/O writes are NOT posted. Memory writes to PCH
normally to the DMI Interface bus. I/O writes are NOT posted. Memory writes to PCH
are posted.
The processor responds to I/O cycles initiated on DMI with an UR status. Upstream
I/O cycles and configuration cycles should never occur. If one does occur, the request
I/O cycles and configuration cycles should never occur. If one does occur, the request
will route as a read to Memory address 000C_0000h so a completion is naturally
generated (whether the original request was a read or write). The transaction will
generated (whether the original request was a read or write). The transaction will
complete with an UR completion status.
For IA-based processors, I/O reads that lie within 8-byte boundaries but cross 4-byte
boundaries are issued from the CPU as 1 transaction. The processor will break this
into 2 separate transactions. I/O writes that lie within 8-byte boundaries but cross 4-
boundaries are issued from the CPU as 1 transaction. The processor will break this
into 2 separate transactions. I/O writes that lie within 8-byte boundaries but cross 4-
byte boundaries are assumed to be split into 2 transactions by the CPU.
1.2.10
Memory Controller Decode Rules and Cross-Bridge
Address Mapping
Address Mapping
VGAA = 000A_0000 – 000A_FFFF
MDA = 000B_0000 – 000B_7FFF
MDA = 000B_0000 – 000B_7FFF
VGAB = 000B_8000 – 000B_FFFF
MAINMEM = 0100_0000 to TOLUD
HIGHMEM = 4 GB to TOM
RECLAIMMEM = RECLAIMBASE to RECLAIMLIMIT
1.2.10.1 Legacy VGA and I/O Range Decode Rules
The legacy 128KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to
IGD (Device #2), and/or to the DMI Interface depending on the programming of the
VGA steering bits. Priority for VGA mapping is constant in that the processor always
IGD (Device #2), and/or to the DMI Interface depending on the programming of the
VGA steering bits. Priority for VGA mapping is constant in that the processor always
decodes internally mapped devices first. Internal to the processor, decode precedence
is always given to IGD. The processor always positively decodes internally mapped
devices, namely the IGD. Subsequent decoding of regions mapped to the DMI
Interface depends on the Legacy VGA configurations bits (VGA Enable).
Interface depends on the Legacy VGA configurations bits (VGA Enable).
1.3
Processor Register Introduction
The CPU internal registers (I/O Mapped, Configuration, and PCI Express Extended
Configuration registers) are accessible by the Host CPU. The registers that reside
Configuration registers) are accessible by the Host CPU. The registers that reside
within the lower 256 bytes of each device can be accessed as Byte, Word (16-bit), or
Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS which can only be
accessed as a Dword. All multi-byte numeric fields use "little-endian" ordering (i.e.,
accessed as a Dword. All multi-byte numeric fields use "little-endian" ordering (i.e.,
lower addresses contain the least significant parts of the field). Registers which reside
in bytes 256 through 4095 of each device may only be accessed using memory
mapped transactions in Dword (32-bit) quantities.