Intel D425 AU80610006252AA User Manual

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Datasheet  

Stolen Memory Size). 
10:8 MB Tseg (TOLUD - GTT Graphics Memory 
Size - Graphics Stolen Memory Size - 8M) to 
(TOLUD - GTT Graphics Memory Size - Graphics 
Stolen Memory Size). 
1:Reserved. 
Once D_LCK has been set, these bits becomes 
read only. 

0 RW/L  0b  Core 

TSEG Enable (T_EN):  
  Enabling of SMRAM memory for Extended 
SMRAM space only. When G_SMRAME = 1 and 
TSEG_EN = 1, the TSEG is enabled to appear in 
the appropriate physical address space. Note 
that once D_LCK is set, this bit becomes read 
only. 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

A0-A1h 

Default Value: 

0001h 

Access: 

 RO; RW/L; 

Size: 16 

bits 

 This Register contains the size of physical memory.  BIOS determines the memory 
size reported to the OS using this Register. 

 

 

15:10 RO 

00h  Core 

Reserved ():  
 

9:0 RW/L  001h Core 

Top of Memory (TOM):  
This register reflects the total amount of 
populated physical memory. This is NOT 
necessarily the highest main memory address 
(holes may exist in main memory address map 
due to addresses allocated for memory mapped 
IO).  These bits correspond to address bits 
35:26 (64MB granularity). Bits 25:0 are 
assumed to be 0.   
MCH determines the base of EP stolen memory 
by subtracting the EP stolen memory size from 
TOM