Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
55
1.5.29
ESMRAMC - Extended System Management RAM Control
B/D/F/Type: 0/0/0/PCI
Address Offset:
9Eh
Default Value:
38h
Access:
RW/L; RWC; RO;
Size: 8
bits
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
Bit Access Default
Value
RST/
PWR
Description
7 RW/L 0b Core
Enable High SMRAM (H_SMRAME):
Controls the SMM memory space location (i.e.
above 1 MB or below 1 MB) When G_SMRAME is
1 and H_SMRAME is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses
within the range 0FEDA0000h to 0FEDBFFFFh
are remapped to DRAM addresses within the
range 000A0000h to 000BFFFFh. Once D_LCK
has been set, this bit becomes read only.
Controls the SMM memory space location (i.e.
above 1 MB or below 1 MB) When G_SMRAME is
1 and H_SMRAME is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses
within the range 0FEDA0000h to 0FEDBFFFFh
are remapped to DRAM addresses within the
range 000A0000h to 000BFFFFh. Once D_LCK
has been set, this bit becomes read only.
6 RWC 0b Core
Invalid SMRAM Access (E_SMERR):
This bit is set when CPU has accessed the
defined memory ranges in Extended SMRAM
(High Memory and T-segment) while not in SMM
space and with the D-OPEN bit = 0. It is
software's responsibility to clear this bit. The
software must write a 1 to this bit to clear it.
This bit is set when CPU has accessed the
defined memory ranges in Extended SMRAM
(High Memory and T-segment) while not in SMM
space and with the D-OPEN bit = 0. It is
software's responsibility to clear this bit. The
software must write a 1 to this bit to clear it.
5 RO 1b Core
SMRAM Cacheable (SM_CACHE):
This bit is forced to '1' by the CPU Uncore.
This bit is forced to '1' by the CPU Uncore.
4 RO 1b Core
L1 Cache Enable for SMRAM (SM_L1):
This bit is forced to '1' by the CPU Uncore.
This bit is forced to '1' by the CPU Uncore.
3 RO 1b Core
L2 Cache Enable for SMRAM (SM_L2):
This bit is forced to '1' by the CPU Uncore.
This bit is forced to '1' by the CPU Uncore.
2:1 RW/L 00b Core
TSEG Size (TSEG_SZ):
Selects the size of the TSEG memory block if
enabled. Memory from the top of DRAM space is
partitioned away so that it may only be accessed
by the processor interface and only then when
the SMM bit is set in the request packet. Non-
SMM accesses to this memory region are sent to
DMI when the TSEG memory block is enabled.
00:1MB Tseg. (TOLUD - GTT Graphics Memory
Size - Graphics Stolen Memory Size - 1M) to
(TOLUD - GTT Graphics Memory Size - Graphics
Stolen Memory Size).
01:2 MB Tseg (TOLUD - GTT Graphics Memory
Size - Graphics Stolen Memory Size - 2M) to
(TOLUD - GTT Graphics Memory Size - Graphics
Selects the size of the TSEG memory block if
enabled. Memory from the top of DRAM space is
partitioned away so that it may only be accessed
by the processor interface and only then when
the SMM bit is set in the request packet. Non-
SMM accesses to this memory region are sent to
DMI when the TSEG memory block is enabled.
00:1MB Tseg. (TOLUD - GTT Graphics Memory
Size - Graphics Stolen Memory Size - 1M) to
(TOLUD - GTT Graphics Memory Size - Graphics
Stolen Memory Size).
01:2 MB Tseg (TOLUD - GTT Graphics Memory
Size - Graphics Stolen Memory Size - 2M) to
(TOLUD - GTT Graphics Memory Size - Graphics