Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
80
Datasheet
1.6.15
C0ODTCTRL - Channel 0 ODT Control
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
29C-29Fh
Default Value:
00000000h
Access:
RO; RW;
Size: 32
bits
ODT controls
Bit Access Default
Value
RST/
PWR
Description
31:12 RO 00000h Core
Reserved ()
11:8 RW 0000b Core
DRAM ODT for Read Commands
(sd0_cr_odt_duration_rd):
Specifies the duration in MDCLKs to assert
DRAM ODT for Read Commands. The Async
value should be used when the Dynamic
Powerdown bit is set. Else use the Sync value.
(sd0_cr_odt_duration_rd):
Specifies the duration in MDCLKs to assert
DRAM ODT for Read Commands. The Async
value should be used when the Dynamic
Powerdown bit is set. Else use the Sync value.
7:4 RW 0000b
Core
DRAM ODT for Write Commands
(sd0_cr_odt_duration_wr):
Specifies the duration in MDCLKs to assert
DRAM ODT for Write Commands. The Async
value should be used when the Dynamic
Powerdown bit is set. Else use the Sync value.
(sd0_cr_odt_duration_wr):
Specifies the duration in MDCLKs to assert
DRAM ODT for Write Commands. The Async
value should be used when the Dynamic
Powerdown bit is set. Else use the Sync value.
3:0 RW 0000b
Core
MCH ODT for Read Commands
(sd0_cr_mchodt_duration):
Specifies the duration in MDCLKs to assert MCH
ODT for Read Commands
(sd0_cr_mchodt_duration):
Specifies the duration in MDCLKs to assert MCH
ODT for Read Commands